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參數(shù)資料
| 型號(hào)： | LXT971ALE |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|單|的CMOS | QFP封裝| 64管腳|塑料 |
| 文件頁數(shù)： | 40/68頁 |
| 文件大?。?/td> | 1177K |
| 代理商： | LXT971ALE |
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LXT9784
—
Low-Power Octal PHY
40
Datasheet
2.6
Hardware Control Interface
The LXT9784 can be configured for unmanaged applications, using external pins (hardware
control) as described in the following paragraphs.
2.6.1
MDI-X
(MDI Crossover)
During RESET, enables the auto-switch feature. If this feature was disabled, then after reset the
MDI-X pin controls the manual MDI/MDI-X switching.
When MDI-X = 1, the MDI port is forced to MDI-X
(cross- over mode).
When MDI-X = 0, the MDI port is forced to MDI
(straight-through mode).
2.6.2
FRCLNK
(Force Link)
During RESET:
When FRCLNK = 1, it
forces good link
(PHY reg17, bit 11),
link integrity
(PHY reg17, bit 1),
and
disables auto-negotiation
(PHY reg0, bit 12)
When FRCLNK = 0, Normal Operation.
If FRCLNK was set, then after reset the FRCLNK pin will control speed selection (PHY reg0, bit
13), where:
When FRCLNK = 1, it forces 100 Mbps.
When FRCLNK = 0, it forces 10 Mbps.
The FRCLNK pin and bit 11 in PHY register 11
’
h are ORed together.
2.6.3
FRC34
(Force 34 Transmit Pattern)
The FRC34 pin and bit 12 in PHY register 11
’
h are ORed together.
2.6.4
BP4B5B
(4B/5B Bypass)
To enter 4B/5B bypass mode, this pin must be set high after the end of reset. During reset, this pin
must be pulled down to ensure proper operation of the LXT9784.
5
Not used
6
TDN
_n
7
Not used
8
Not used
Table 15. Crossed-over Pin Assignments
Contact
MDI Signal
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