- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄369886 > LXT971ALE LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC PDF資料下載
參數(shù)資料
| 型號： | LXT971ALE |
| 英文描述： | LAN TRANSCEIVER|SINGLE|CMOS|QFP|64PIN|PLASTIC |
| 中文描述： | 網(wǎng)絡(luò)收發(fā)器|單|的CMOS | QFP封裝| 64管腳|塑料 |
| 文件頁數(shù)： | 31/68頁 |
| 文件大小： | 1177K |
| 代理商： | LXT971ALE |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁當前第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁
Low-Power Octal PHY
—
LXT9784
Datasheet
31
2.3.1.3
Baseline Wander Correction
The baseline wander effect is the wandering of the DC offset of the receive signal. The wander of
the DC offset happens when the 100BASE-TX data is not DC-balanced. Baseline wander can
greatly reduce BER performance. The LXT9784 Equalizer has an automatic baseline wander
correction circuit, thereby preserving outstanding BER performance in case of extreme baseline
wander conditions.
2.3.1.4
Decoder
The LXT9784 PHYs first convert the data from the clock recovery circuitry to NRZ format. The
NRZ serial data stream is assembled to 5-bit symbols, de-scrambled and aligned to symbol
boundaries. The de-scrambling is based on synchronization to the transmitted Idle pattern
generated by an 11-bit LFSR during idle. The data is then decoded at the 5B/4B decoder.
2.3.1.5
100BASE-TX Receive Framing
The LXT9784 PHYs do not differentiate between the fields of the MAC frame containing
preamble, SFD, data and CRC. During 100 Mbps reception, the PHY detects Start-of-Stream
Delimiter (SSD) (/J/K/) and End-of-Stream Delimiter ESD) (/T/R/) pairs. The PHY strips those
symbols from the data stream before passing the packet to the MAC. CRSDV
n
is asserted on a
detection of a non-idle symbol.
2.3.1.6
100BASE-TX RMII Data Reception
When the receive medium is idle, CRSDV
n
is de-asserted and the data on RXD
n_
<1:0> is
“
00
”
.
When carrier is detected, CRSDV
n
signal asserts asynchronously. After the internal FIFO is half
full, the PHY transfers two bits of recovered data on RXD
n_
<1:0> at each clock period,
synchronous to MCLK.
If the PHY has additional bits to present on RXD
n_
<1:0> (accumulated in the FIFO) after
CRSDV
n
initial de-assertion, then CRSDV
n
toggles at 25 MHz, starting on a nibble boundary.
See
Figure 5
If false carrier is detected (bad SSD), then RXD
n_
<1:0> will be
“
10
”
until the end of the receive
event. See
Figure 6
.
2.3.1.7
100BASE-TX SMII Data Reception
The data is signaled in ten-bit segments, where each segment represents a new byte of data. Each
segment is delimited by a SYNC pulse (every 10 clocks).
RXD_[7:0] in the serial bit stream are used to convey packet data, receive error status from the
previous frame, and PHY status, decoded by two SMII control bits (CRS and RX_DV). See
Table
12
for bit definitions.
Figure 7
shows the SMII receive data stream.
When the receive medium is busy receiving a frame, SMII control bit CRS is asserted. RX_ER
(inter-frame status bit RXD0) is asserted if during a frame reception the internal FIFO overflows or
underflows.
If false carrier is detected (bad Start-of-Stream Delimiter), then inter-frame status bit RXD6 is
asserted.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| LXT974QC | LAN Transceiver |
| LXT975QC | LAN Transceiver |
| LXT9761 | Interface IC |
| LXT9761HC | LAN TRANSCEIVER|HEX|QFP|208PIN|PLASTIC |
| LXT9762 | Interface IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LXT971LC | 制造商:Intel 功能描述: |
| LXT972A | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972ALC | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:3.3V Dual-Speed Fast Ethernet Transceiver Datasheet |
| LXT972LCHFB8 | 制造商:LEVEL_ONE 功能描述: |
| LXT972M | 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Single-Port 10/100 Mbps PHY Transceiver |
發(fā)布緊急采購，3分鐘左右您將得到回復。