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| 型號： | LTC4268IDKD-1#PBF |
| 廠商： | Linear Technology |
| 文件頁數(shù)： | 38/46頁 |
| 文件大?。?/td> | 419K |
| 描述： | IC PD HIGH POWER W/CNTRL 32-DFN |
| 產(chǎn)品培訓(xùn)模塊： | Power over Ethernet |
| 標(biāo)準(zhǔn)包裝： | 52 |
| 類型： | 以太網(wǎng)供電開關(guān)（PoE） |
| 應(yīng)用： | 遠(yuǎn)程外設(shè)（工業(yè)控制，相機(jī)，數(shù)據(jù)訪問） |
| 內(nèi)部開關(guān)： | 是 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 32-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 32-DFN（7x4）裸露焊盤 |
| 包裝： | 管件 |
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LTC4268-1
38
42681fc
Power MOSFET Selection
The power MOSFETs are selected primarily on the criteria of
on resistance R
DS(ON)
, input capacitance, drain-to-source
breakdown voltage (BV
DSS
), maximum gate voltage (V
GS
)
and maximum drain current (ID
(MAX)
).
For the primary-side power MOSFET, the peak current is:
I
PK(PRI)
=
P
IN
V
IN(MIN)
DC
MAX
1+
X
MIN
2
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
where X
MIN
is peak-to-peak current ratio as defined
earlier. For each secondary-side power MOSFET, the peak
current is:
I
PK(SEC)
=
I
OUT
1DC
MAX
1+
X
MIN
2
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
Select a primary-side power MOSFET with a BV
DSS
greater
than:
BV
DSS
eI
PK
L
LKG
C
P
+ V
IN(MAX)
+
V
OUT(MAX)
N
SP
where N
SP
reflects the turns ratio of that secondary-to
primary winding. L
LKG
is the primary-side leakage induc-
tance and C
P
is the primary-side capacitance (mostly from
the drain capacitance (C
OSS
) of the primary-side power
MOSFET). A snubber may be added to reduce the leakage
inductance as discussed.
For each secondary-side power MOSFET, the BV
DSS
should
be greater than:
BV
DSS
e V
OUT
+ V
IN(MAX)
" N
SP
applicaTions inForMaTion
Choose the primary side MOSFET R
DS(ON)
at the nominal
gate drive voltage (7.5V). The secondary side MOSFET
gate drive voltage depends on the gate drive method.
Primary side power MOSFET RMS current is given by:
I
RMS(PRI)
=
P
IN
V
IN(MIN)
DC
MAX
For each secondary-side power MOSFET RMS current is
given by:
I
RMS(SEC)
=
I
OUT
1DC
MAX
Calculate MOSFET power dissipation next. Because the
primary-side power MOSFET operates at high V
DS
, a
transition power loss term is included for accuracy. C
MILLER
is the most critical parameter in determining the transition
loss, but is not directly specified on the data sheets.
C
MILLER
is calculated from the gate charge curve included
on most MOSFET data sheets (Figure 17).
The flat portion of the curve is the result of the Miller
(gate-to-drain) capacitance as the drain voltage drops.
The Miller capacitance is computed as:
C
MILLER
=
Q
B
Q
A
V
DS
The curve is done for a given V
DS
. The Miller capacitance
for different V
DS
voltages are estimated by multiplying the
computed C
MILLER
by the ratio of the application V
DS
to
the curve specified V
DS
.
Q
A
V
GS
a
b
42681 F18
Q
B
MILLER EFFECT
GATE CHARGE (Q
G
)
Figure 18. Gate Charge Curve
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| LTC4269CDKD-1#PBF | 功能描述:IC PD/OPTO FLYBACK CTRLR 32-DFN RoHS:是 類別:集成電路 (IC) >> PMIC - 熱交換 系列:- 標(biāo)準(zhǔn)包裝:50 系列:- 類型:熱交換控制器 應(yīng)用:-48V 遠(yuǎn)程電力系統(tǒng)，AdvancedTCA ? 系統(tǒng)，高可用性 內(nèi)部開關(guān):無 電流限制:可調(diào) 電源電壓:11.5 V ~ 14.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:10-TFSOP，10-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:10-MSOP 包裝:管件 |
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