參數(shù)資料
型號(hào): LTC4268IDKD-1#PBF
廠商: Linear Technology
文件頁(yè)數(shù): 31/46頁(yè)
文件大?。?/td> 419K
描述: IC PD HIGH POWER W/CNTRL 32-DFN
產(chǎn)品培訓(xùn)模塊: Power over Ethernet
標(biāo)準(zhǔn)包裝: 52
類型: 以太網(wǎng)供電開(kāi)關(guān)(PoE)
應(yīng)用: 遠(yuǎn)程外設(shè)(工業(yè)控制,相機(jī),數(shù)據(jù)訪問(wèn))
內(nèi)部開(kāi)關(guān):
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFDFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 32-DFN(7x4)裸露焊盤(pán)
包裝: 管件
42681fc
LTC4268-1
31
applicaTions inForMaTion
Transformer Core Selection
Once L
P
 is known, the type of transformer is selected.
High efficiency converters use ferrite cores to minimize
core loss. Actual core loss is independent of core size for
a fixed inductance, but decreases as inductance increases.
Since increased inductance is accomplished through more
turns of wire, copper losses increase. Thus transformer
design balances core and copper losses. Remember that
increased winding resistance will degrade cross regulation
and increase the amount of load compensation required.
The main design goals for core selection are reducing
copper losses and preventing saturation. Ferrite core
material saturates hard, rapidly reducing inductance
when the peak design current is exceeded. This results
in an abrupt increase in inductor ripple current and,
consequently, output voltage ripple. Do not allow the core
to saturate! The maximum peak primary current occurs
at minimum V
IN
:
I
PK
=
P
IN
V
IN(MIN)
DC
MAX
1+
X
MIN
2
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
now:
DC
MAX
=
1
1+
N  V
IN MIN
(   )
V
OUT
=
1
1+
1
8
41
5
= 49.4%
X
MIN
=
V
IN(MIN)
DC
MAX
(
)
2
f
OSC
L
P
P
IN
=
41  49.4%
(
)
2
200kHz  260礖  29.5W
=  .2  7
Using the example numbers leads to:
 
I
PK
=
29.5W
41  0.494
1+
0.267
2
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=1.65A
Multiple Outputs
One advantage that the flyback topology offers is that
additional output voltages can be obtained simply by adding
windings. Designing a transformer for such a situation is
beyond the scope of this document. For multiple windings,
realize that the flyback winding signal is a combination of
activity on all the secondary windings. Thus load regulation
is affected by each windings load. Take care to minimize
cross regulation effects.
Setting Feedback Resistive Divider
The expression for V
OUT
 developed in the Operation section
is rearranged to yield the following expression for the
feedback resistors:
 
R1=R2
V
OUT
+I
SEC
ESR+R
DS(ON)
(
)
?/DIV>
?/DIV>
?/DIV>
?/DIV>
V
FB
N
SF
1
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
Continuing the example, if ESR + R
DS(ON)
 = 8mW, R2 =
3.32k, then:
 
R1=3.32k
5+5.3  0.008
1.237  1/ 3
1
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
=37.28k
choose 37.4k.
It is recommended that the Thevenin impedance of the
resistive divider (R1||R2) is roughly 3k for bias current
cancellation and other reasons.
Current Sense Resistor Considerations
The external current sense resistor is used to control peak
primary switch current, which controls a number of key
converter characteristics including maximum power and
external component ratings. Use a noninductive current
sense resistor (no wire-wound resistors). Mounting the
resistor directly above an unbroken ground plane connected
with wide and short traces keeps stray resistance and
inductance low.
The dual sense pins allow for a full Kelvin connection. Make
sure that SENSE+ and SENSE are isolated and connect
close to the sense resistor.
Peak current occurs at 100mV of sense voltage V
SENSE
. So
the nominal sense resistor is V
SENSE
/I
PK
. For example, a
peak switch current of 10A requires a nominal sense resistor
of 0.010W Note that the instantaneous peak power in the
sense resistor is 1W, and that it is rated accordingly. The
use of parallel resistors can help achieve low resistance,
low parasitic inductance and increased power capability.
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