參數(shù)資料
型號: LTC4268IDKD-1#PBF
廠商: Linear Technology
文件頁數(shù): 33/46頁
文件大?。?/td> 419K
描述: IC PD HIGH POWER W/CNTRL 32-DFN
產(chǎn)品培訓(xùn)模塊: Power over Ethernet
標(biāo)準(zhǔn)包裝: 52
類型: 以太網(wǎng)供電開關(guān)(PoE)
應(yīng)用: 遠(yuǎn)程外設(shè)(工業(yè)控制,相機(jī),數(shù)據(jù)訪問)
內(nèi)部開關(guān):
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 32-WFDFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 32-DFN(7x4)裸露焊盤
包裝: 管件
42681fc
LTC4268-1
33
applicaTions inForMaTion
Setting Frequency
The switching frequency of the LTC4268-1 is set by an
external capacitor connected between the OSC pin and
ground. Recommended values are between 200pF and
33pF, yielding switching frequencies between 50kHz and
250kHz. Figure 15shows the nominal relationship between
external capacitance and switching frequency. Place the
capacitor as close as possible to the IC and minimize OSC
trace length and area to minimize stray capacitance and
potential noise pickup.
You can synchronize the oscillator frequency to an external
frequency. This is done with a signal on the SYNC pin. Set
the LTC4268-1 frequency 10% slower than the desired
external frequency using the OSC pin capacitor, then use
a pulse on the SYNC pin of amplitude greater than 2V
and with the desired frequency. The rising edge of the
SYNC signal initiates an OSC capacitor discharge forcing
primary MOSFET off (PG voltage goes low). If the oscillator
frequency is much different from the sync frequency,
problems may occur with slope compensation and system
stability. Keep the sync pulse width greater than 500ns.
Selecting Timing Resistors
There are three internal one-shot times that are
programmed by external application resistors: minimum on
time, enable delay time and primary MOSFET turn-on delay.
These are all part of the isolated flyback control technique,
and their functions are previously outlined in the Theory
of Operation section. The following information should
help in selecting and/or optimizing these timing values.
Minimum Output Switch On Time (t
ON(MIN)
)
Minimum on time is the programmable period during which
current limit is blanked (ignored) after the turn on of the
primary side switch. This improves regulator performance
by eliminating false tripping on the leading edge spike in
the switch, especially at light loads. This spike is due to
both the gate/source charging current and the discharge of
drain capacitance. The isolated flyback sensing requires a
pulse to sense the output. Minimum on time ensures that
the output switch is always on a minimum time and that
there is always a signal to close the loop. The LTC4268-1
does not employ cycle skipping at light loads. Therefore,
C
OSC
 (pF)
 
30
50
100
200
300
100
200
42681 F15
Figure 15. f
OSC
 vs OSC Capacitor Values
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