參數(shù)資料
型號: LTC4252A-1IMS#TRPBF
廠商: Linear Technology
文件頁數(shù): 24/36頁
文件大小: 328K
描述: IC CNTRLR HOTSWAP NEGVOLT 10MSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
24
425212fe
For more information www.linear.com/LTC4252-1
applicaTions inForMaTion
Undervoltage Timing
In Figure 11 when UV pin drops below V
UVLO
 (time point?),
the LTC4252 shuts down with TIMER, SS and GATE all
pulling low. If current has been flowing, the SENSE pin
voltage decreases to zero as GATE collapses. When UV
recovers and clears V
UVHI
 (time point 2), an initial timer
cycle begins followed by a GATE start-up cycle.
V
IN
 Undervoltage Lockout Timing
The V
IN
 undervoltage lockout comparator, UVLO, has a
similar timing behavior as the UV pin timing except it looks
for V
IN
 < (V
LKO
  V
LKH
) to shut down and V
IN
 > V
LKO
 to
start. In an undervoltage lockout condition, both UV and
OV comparators are held off. When V
IN
 exits undervoltage
lockout, the UV and OV comparators are enabled.
Undervoltage Timing with Overvoltage Glitch
In Figure 12, both UV and OV pins are connected together.
When UV clears V
UVHI
 (time point 1), an initial timing
cycle starts. If the system bus voltage overshoots V
OVHI
 
as shown at time point 2, TIMER discharges. At time point
3, the supply voltage recovers and drops below the V
OVLO
 
threshold. The initial timing cycle restarts, followed by a
GATE start-up cycle.
Overvoltage Timing
During normal operation, if the OV pin exceeds V
OVHI
 as
shown at time point 1 of Figure 13, the TIMER and PWRGD
status are unaffected. Nevertheless, SS and GATE pull down
and the load is disconnected. At time point 2, OV recovers
and drops below the V
OVLO
 threshold. A GATE start-up
cycle begins. If the overvoltage glitch is long enough to
deplete the load capacitor, a full start-up cycle as shown
between time points 4 through 7 may occur.
Circuit Breaker Timing
In Figure 14a, the TIMER capacitor charges at 230礎(chǔ) if
the SENSE pin exceeds V
CB
 but V
DRN
 is less than 5V . If
the SENSE pin drops below V
CB
 before TIMER reaches
UV
TIMER
GATE
SENSE
SS
DRAIN
PWRGD
5.8礎(chǔ)
58礎(chǔ)
5.8礎(chǔ)
5.8礎(chǔ)
58礎(chǔ)
UV DROPS BELOW V
UVLO
. GATE, SS AND TIMER ARE PULLED DOWN, PWRGD RELEASES
1
2
3 4 56    7   89
TIMER CLEARS V
TMRL
, CHECK GATE < V
GATEL
, SENSE < V
CB
 AND SS < 20 " V
OS
1011
425212 F11
UV CLEARS V
UVHI
, CHECK OV CONDITION, GATE < V
GATEL
, SENSE < V
CB
, SS < 20 " V
OS
 AND TIMER < V
TMRL
V
ACL
V
CB
230礎(chǔ) + 8 " I
DRN
20 " V
OS
V
IN
  V
GATEH
V
DRNL
V
DRNCL
20 " (V
CB
 + V
OS
)
20 " (V
ACL
 + V
OS
)
V
GATEL
V
TMRL
V
TMRH
V
UVHI
V
UVLO
GATE
START-UP
INITIAL TIMING
Figure 11. Undervoltage Timing (All Waveforms Are Referenced to V
EE
)
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