參數(shù)資料
型號: LTC4252A-1IMS#TRPBF
廠商: Linear Technology
文件頁數(shù): 17/36頁
文件大?。?/td> 328K
描述: IC CNTRLR HOTSWAP NEGVOLT 10MSOP
標(biāo)準(zhǔn)包裝: 2,500
類型: 熱交換控制器
應(yīng)用: 通用
內(nèi)部開關(guān):
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 10-TFSOP,10-MSOP(0.118",3.00mm 寬)
供應(yīng)商設(shè)備封裝: 10-MSOP
包裝: 帶卷 (TR)
LTC4252-1/LTC4252-2
LTC4252A-1/LTC4252A-2
17
425212fe
For more information www.linear.com/LTC4252-1
applicaTions inForMaTion
2.5% or more will eventually trip the circuit breaker and
shut down the LTC4252. Figure 5 shows the circuit breaker
response time in seconds normalized to 1礔 for I
DRN
 =
0礎(chǔ). The asymmetric charging and discharging of C
T
 is
a fair gauge of MOSFET heating.
The normalized circuit response time is estimated by
 
t
C
T
(礔)
=
4
235.8+8"I
DRN
(
)
"D5.8
?/DIV>
?/DIV>
?/DIV>
?/DIV>
 
(4)
SHUTDOWN COOLING CYCLE
For the LTC4252-1 (latchoff version), TIMER latches high
with a 5.8礎(chǔ) pull-up after the circuit breaker fault TIMER
reaches 4V . For the LTC4252-2 (automatic retry version),
a shutdown cooling cycle begins if TIMER reaches the
4V threshold. TIMER starts with a 5.8礎(chǔ) pull-down until
it reaches the 1V threshold. Then, the 5.8礎(chǔ) pull-up turns
back on until TIMER reaches the 4V threshold. Four 5.8礎(chǔ)
pull-down cycles and three 5.8礎(chǔ) pull-up cycles occur
between the 1V and 4V thresholds, creating a time interval
given by:
 
t
SHUTDOWN
=
7"3V"C
T
5.8礎(chǔ)
 
(5)
At the 1V threshold of the last pull-down cycle, a GATE
ramp-up is attempted.
SOFT-START
Soft-start limits the inrush current profile during GATE
start-up. Unduly long soft-start intervals can exceed the
MOSFETs SOA rating if powering up into an active load.
If SS floats, an internal current source ramps SS from 0V
to 2.2V for the LTC4252 or 0V to 1.4V for the LTC4252A
in about 230祍. Connecting an external capacitor C
SS
 
from SS to ground modifies the ramp to approximate an
RC response of:
 
V
SS
(t)HV
SS
"  1e

t
R
SS
" C
SS
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
?/DIV>
 
(6)
An internal resistive divider (95k/5k for the LTC4252 or
47.5k/2.5k for the LTC4252A) scales V
SS
(t) down by 20
times to give the analog current limit threshold:
 
V
ACL
(t)=
V
SS
(t)
20
V
OS
 
(7)
This allows the inrush current to be limited to V
ACL
(t)/R
S
.
The offset voltage, V
OS
 (10mV), ensures C
SS
 is sufficiently
discharged and the ACL amplifier is in current limit before
GATE start-up. SS is pulled low under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out.
GATE
GATE is pulled low to V
EE
 under any of the following
conditions: in UVLO, in an undervoltage condition, in an
overvoltage condition, during the initial timing cycle or
when the circuit breaker fault times out. When GATE turns
on, a 58礎(chǔ) current source charges the MOSFET gate and
any associated external capacitance. V
IN
 limits the gate
drive to no more than 14.5V .
Gate-drain capacitance (C
GD
) feedthrough at the first
abrupt application of power can cause a gate-source
voltage sufficient to turn on the MOSFET . A unique circuit
pulls GATE low with practically no usable voltage at V
IN
 
FAULT DUTY CYCLE (%)
0
20
40
60
80
100
10
1
0.1
0.01
=
4
[(235.8 + 8 " I
DRN
) " D  5.8]
t
C
T
(礔)
I
DRN
 = 0礎(chǔ)
Figure 5. Circuit-Breaker Response Time
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