
LTC4099
4099fd
downtheSDAlineduringthewriteacknowledgeclock
pulsesothatitisastableLOWduringtheHIGHperiod
ofthisclockpulse.
WhentheLTC4099isreadfrom,itreleasestheSDAline
sothatthemastermayacknowledgereceiptofthedata.
SincetheLTC4099onlytransmitsonebyteofdata,amaster
notacknowledgingthedatasentbytheLTC4099hasno
specificconsequenceontheoperationoftheI2Cport.
However,withoutareadacknowledgefromthemaster,a
pendinginterruptfromtheLTC4099willnotbecleared
andtheIRQpinwillnotbereleased.
Slave Address
TheLTC4099respondstoa7-bitaddresswhichhasbeen
factory programmed to 0b0001001[R/W]. The LSB of
theaddressbyte,knownastheread/writebit,shouldbe
0whenwritingdatatotheLTC4099,and1whenreading
datafromit.Consideringtheaddressan8-bitword,then
thewriteaddressis0x12,andthereadaddressis0x13.
TheLTC4099willacknowledgebothitsreadandwrite
addresses.
Sub-Addressed Writing
TheLTC4099hasthreecommandregistersforcontrol
input. They are accessed by the I2C port via a sub-
addressedwritingsystem.
EachwritecycleoftheLTC4099consistsofexactlythree
bytes.ThefirstbyteisalwaystheLTC4099’swriteaddress.
ThesecondbyterepresentstheLTC4099’ssubaddress.
Thesubaddressisapointerwhichdirectsthesubsequent
databytewithintheLTC4099.Thethirdbyeconsistsof
thedatatobewrittentothelocationpointedtobythe
subaddress.TheLTC4099containscontrolregistersat
onlythreesubaddresslocations:0x00,0x01and0x02.
OnlythetwoLSBsofthesubaddressbytearedecoded,
theremainingbitsaredon’t-cares.Therefore,awriteto
subaddress0x06forexample,iseffectivelyawriteto
subaddress0x02.
Bus Write Operation
The master initiates communication with the LTC4099
withaSTARTconditionandtheLTC4099’swriteaddress.
IftheaddressmatchesthatoftheLTC4099,theLTC4099
returnsanacknowledge.Themastershouldthendeliver
thesubaddress.Again,theLTC4099acknowledgesand
thecycleisrepeatedforthedatabyte.Thedatabyteis
transferredtoaninternalholdinglatchuponthereturnof
itsacknowledgebytheLTC4099.Thisproceduremustbe
repeatedforeachsubaddressthatrequiresnewdata.After
oneormorecyclesof[ADDRESS][SUB-ADDRESS][DATA],
themastermayterminatethecommunicationwithaSTOP
condition.Alternatively,arepeatSTARTconditioncanbe
initiatedbythemasterandanotherchipontheI2Cbuscan
beaddressed.Thiscyclecancontinueindefinitely,andthe
LTC4099willrememberthelastinputofvaliddatathatit
received.Onceallchipsonthebushavebeenaddressed
andsentvaliddata,aglobalSTOPcanbesentandthe
LTC4099willupdateitscommandlatcheswiththedata
thatithadreceived.
Bus Read Operation
ThebusmasterreadsthestatusoftheLTC4099witha
STARTconditionfollowedbytheLTC4099readaddress.If
thereadaddressmatchesthatoftheLTC4099,theLTC4099
returnsanacknowledge.Followingtheacknowledgement
ofitsreadaddress,theLTC4099returnsonebitofstatus
informationforeachofthenexteightclockcycles.ASTOP
commandisnotrequiredforthebusreadoperation.
Input Data
Table1illustratesthethreedatabytesthatmaybewrit-
tentotheLTC4099.Thefirstbyteatsubaddress0x00
controlsthethreeinputcurrentlimitbitsILIM2-ILIM0,the
threebatterychargecurrentcontrolbitsICHARGE2-ICHARGE0
and the two C/x state-of-charge indication control bits
COVERX1andCOVERX0.
Theinputcurrentlimitsettingsaredecodedaccordingto
Table2.Thistableindicatesthemaximumcurrentthatwill
bedrawnfromtheVBUSpinintheeventthattheloadat
VOUT(batterychargerplussystemload)exceedsthepower
available.Anyadditionalpowerwillbedrawnfromthebat-
tery.Thedefaultstatefortheinputcurrentlimitsettingis
000,representingthelowpower100mAUSBsetting.
operaTion