參數(shù)資料
型號: LTC1873EG
廠商: LINEAR TECHNOLOGY CORP
元件分類: 穩(wěn)壓器
英文描述: Quadruple 2-Input Positive-AND Gate 14-TSSOP -40 to 85
中文描述: 5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO28
封裝: 0.209 INCH, PLASTIC, SSOP-28
文件頁數(shù): 27/32頁
文件大?。?/td> 308K
代理商: LTC1873EG
27
LTC1873
TRANSIENT RESPONSE
Transient response is the other half of the regulation
equation. The LTC1873 can keep the DC output voltage
constant to within 1% when averaged over hundreds of
cycles. Over just a few cycles, however, the external
components conspire to limit the speed that the output can
move. Consider our typical 5V to 1.5V circuit, subjected to
a 1A to 5A load transient. Initially, the loop is in regulation
and the DC current in the output capacitor is zero.
Suddenly, an extra 4A start flowing out of the output
capacitor while the inductor is still supplying only 1A. This
sudden change will generate a (4A)(C
ESR
)voltage step at
the output; with a typical 0.015
output capacitor ESR,
this is a 60mV step at the output, or 4% (for a 1.5V output
voltage).
Very quickly, the feedback loop will realize that something
has changed and will move at the bandwidth allowed by
the external compensation network towards a new duty
cycle. If the bandwidth is set to 50kHz, the COMP pin will
get to 60% of the way to 90% duty cycle in 3
μ
s. Now the
inductor is seeing 3.5V across itself for a large portion of
the cycle, and its current will increase from 1A at a rate set
by di/dt = V/L. If the inductor value is 0.5
μ
H, the di/dt will
be 3.5V/0.5
μ
H or 7A/
μ
s. Sometime in the next few micro-
seconds after the switch cycle begins, the inductor current
will have risen to the 5A level of the load current and the
output capacitor will stop losing charge.
Note that the output voltage will stop dropping before the
inductor current reaches this new output current level.
Recall that any practical output capacitor looks like a pure
capacitance in series with some amount of ESR. When a
load transient hits, virtually all of the initial voltage drop at
the output is due to IR drop across the ESR. The output
capacitance begins to discharge at the same time and
continues until the inductor current rises to match the new
output current level.
The output voltage, however, will turn around and start
heading the right way before this happens. The next time
the top MOSFET turns on, the inductor current will begin
increasing linearly. This increasing current flows almost
entirely into the capacitor, going through the ESR as it
does so (Figure 15). Positive di/dt in the inductor causes
positive dv/dt in the ESR, regardless of what the “pure”
capacitance is doing. The output voltage will turn around
when the positive dv/dt across the ESR exceeds the
negative dv/dt across the pure capacitance. If the expected
load step (
I) is known, an optimum inductor value can be
chosen:
L
V
V
C
ESR
I
IN
OUT
(
)
Making L smaller than this optimum value yields little or no
improvement in transient response. As the output voltage
recovers, the inductor current will briefly rise above the
level of the output current to replenish the charge lost from
the output capacitor. With a properly compensated loop,
the entire recovery time will be inside of 10
μ
s.
Most loads care only about the maximum deviation from
ideal, which occurs somewhere in the first two cycles after
the load step hits. During this time, the output capacitor
does all the work until the inductor and control loop regain
control. The initial drop (or rise if the load steps down) is
entirely controlled by the ESR of the capacitor and amounts
to most of the total voltage drop. To minimize this drop,
reduce the ESR as much as possible by choosing low ESR
capacitors and/or paralleling multiple capacitors at the
output. The capacitance value accounts for the rest of the
voltage drop until the inductor current rises. With most
output capacitors, several devices paralleled to get the
ESR down will have so much capacitance that this drop
term is negligible. Ceramic capacitors are an exception; a
small ceramic capacitor can have suitably low ESR with
relatively small values of capacitance, making this second
drop term significant.
Optimizing Loop Compensation
Loop compensation has a fundamental impact on tran-
sient recovery time, the time it takes the LTC1873 to
recover after the output voltage has dropped due to
output capacitor ESR. Optimizing loop compensation
entails maintaining the highest possible loop bandwidth
while ensuring loop stability. The Feedback Component
APPLICATIOU
W
U
U
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