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參數(shù)資料
| 型號(hào)： | LTC1873EG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Quadruple 2-Input Positive-AND Gate 14-TSSOP -40 to 85 |
| 中文描述： | 5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 308K |
| 代理商： | LTC1873EG |
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16
LTC1873
normal opera
tion. The MAX comparator will act as usual,
turning on QB until output is within range and then
allowing the loop to resume normal operation. FAULT can
also be pulled down with external open-collector logic to
restart a fault-latched LTC1873 as an alternative to recy-
cling the power. Note that this will not reset the internal
latch; if the external pull-down is released, the LTC1873
will reenter FAULT mode. To reset the latch, pull both RUN/
SS pins low simultaneously or cycle the power.
VID Considerations
Some applications change the VID codes at channel 1 on
the fly. This is possible with the LTC1873, but care must
be taken to avoid tripping the overvoltage fault circuit.
Stepping the voltage upwards abruptly is safe, but step-
ping down quickly by more than 15% can leave the system
in a state where the output voltage is still at the old higher
level, but the feedback node is set to expect a new,
substantially lower voltage. If this condition persists for
more than 25
μ
s, the overvoltage fault circuitry will activate
and latch off the LTC1873.
The simplest solution is to disable the fault circuit by
grounding the FAULT pin. Systems that must keep the
fault circuit active should ensure that the output voltage is
never programmed to step down by more than 15% in any
single step. A safe strategy is to step the output down by
10% or less at a time and wait for the output to settle to the
new value before taking subsequent steps. Regardless of
the state of the FAULT pin, the load is always protected
against overvoltage faults by the +5% MAX comparator.
EXTERNAL COMPONENT SELECTION
POWER MOSFETs
Getting peak efficiency out of the LTC1873 depends strongly
on the external MOSFETs used. The LTC1873 requires at
least two external MOSFETs per side—more if one or
more of the MOSFETs are paralleled to lower on-resis-
tance. To work efficiently, these MOSFETs must exhibit
low R
DS(ON)
at 5V V
GS
(3.3V V
GS
if the PV
CC
input supply
is 3.3V) to minimize resistive power loss while they are
conducting current. They must also have low gate charge
to minimize transition losses during switching. On the
other hand, voltage breakdown requirements in a typical
LTC1873 circuit are pretty tame: the 7V maximum input
voltage limits the V
DS
and V
GS
the MOSFETs can see to
safe levels for most devices.
Low R
DS(ON)
R
DS(ON)
calculations are pretty straightforward. R
DS(ON)
is
the resistance from the drain to the source of the MOSFET
when the gate is fully on. Many MOSFETs have R
DS(ON)
specified at 4.5V gate drive—this is the right number to
use in LTC1873 circuits running from a 5V supply. As
current flows through this resistance while the MOSFET is
on, it generates I
2
R watts of heat, where I is the current
flowing (usually equal to the output current) and R is the
MOSFET R
DS(ON)
. This heat is only generated when the
MOSFET is on. When it is off, the current is zero and the
power lost is also zero (and the other MOSFET is busy
losing power).
This lost power does two things: it subtracts from the
power available at the output, costing efficiency, and it
makes the MOSFET hotter—both bad things. The effect is
worst at maximum load when the current in the MOSFETs
and thus the power lost are at a maximum. Lowering
R
DS(ON)
improves heavy load efficiency at the expense of
additional gate charge (usually) and more cost (usually).
Proper choice of MOSFET R
DS(ON)
becomes a trade-off
between tolerable efficiency loss, power dissipation and
cost. Note that while the lost power has a significant effect
on system efficiency, it only adds up to a watt or two in a
typical LTC1873 circuit, allowing the use of small, surface
mount MOSFETs without heat sinks.
Gate Charge
Gate charge is the amount of charge (essentially, the
number of electrons) that the LTC1873 needs to put into
the gate of an external MOSFET to turn it on. The easiest
way to visualize gate charge is to think of it as a capacitance
from the gate pin of the MOSFET to SW (for QT) or to PGND
(for QB). This capacitance is composed of MOSFET chan-
nel charge, actual parasitic drain-source capacitance and
Miller-multiplied gate-drain capacitance, but can be
approximated as a single capacitance from gate to source.
Regardless of where the charge is going, the fact remains
APPLICATIOU
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相關(guān)PDF資料 |
PDF描述 |
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| LTC1873 | Dual 550kHz Synchronous 2-Phase Switching Regulator Controller with 5-Bit VID(550kHz,雙 路,同步2相開關(guān)穩(wěn)壓器(帶5位VID)) |
| LTC1874 | Dual Constant Frequency Current Mode Step-Down DC/DC Controller(雙路(3.3V,1.8V輸出）恒定頻率，電流模式，步降DC/DC控制器) |
| LTC1874EGN | Quadruple 2-Input Positive-AND Gate 14-VQFN -40 to 85 |
| LTC1875 | 15mA Quiescent Current 1.5A Monolithic Synchronous Step-Down Regulator |
| LTC1875EGN | 15mA Quiescent Current 1.5A Monolithic Synchronous Step-Down Regulator |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LTC1873EG#PBF | 功能描述:IC REG CTRLR BUCK PWM VM 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC1873EG#TR | 功能描述:IC REG CTRLR BUCK PWM VM 28-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC1873EG#TRPBF | 功能描述:IC REG CTRLR BUCK PWM VM 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC1874EGN | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
| LTC1874EGN#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標(biāo)準(zhǔn)包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
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