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參數(shù)資料
| 型號： | LTC1873EG |
| 廠商： | LINEAR TECHNOLOGY CORP |
| 元件分類： | 穩(wěn)壓器 |
| 英文描述： | Quadruple 2-Input Positive-AND Gate 14-TSSOP -40 to 85 |
| 中文描述： | 5 A SWITCHING CONTROLLER, 750 kHz SWITCHING FREQ-MAX, PDSO28 |
| 封裝： | 0.209 INCH, PLASTIC, SSOP-28 |
| 文件頁數(shù)： | 15/32頁 |
| 文件大?。?/td> | 308K |
| 代理商： | LTC1873EG |
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15
LTC1873
FCB Pin
In some circumstances, it is desirable to control or disable
discontinuous and Burst Mode operations. The FCB (Force
Continuous Bar) pin allows the user to do this. When the
FCB pin is high, the LTC1873 is allowed to enter discon-
tinuous and Burst Mode operations at either side as
required. If FCB is taken low, discontinuous and Burst
Mode operations are disabled and both sides of the
LTC1873 run in continuous mode regardless of load. This
does not affect output regulation but does reduce effi-
ciency at low output currents. The FCB pin threshold is
specified at 0.8V
±
50mV, and includes 20mV of hyster-
esis, allowing it to be used as a precision small-signal
comparator.
Paralleling Outputs
Synchronous regulators (like the LTC1873) are known for
their bullheadedness when their outputs are paralleled
with other regulators. In particular, a synchronous regu-
lator paralleled with another regulator whose output is
slightly higher (perhaps just by millivolts) will happily sink
amps of current attempting to pull its own output back
down to what it thinks is the right value.
The LTC1873 discontinuous mode allows it to be paral-
leled with another regulator without fighting. A typical
system might use the LTC1873 as a primary regulator and
a small LDO as a backup regulator to keep SRAM alive
when the main power is off. When the LTC1873 is shut
down (by pulling RUN/SS to ground), both QT and QB turn
off and the output goes into a high impedance state,
allowing the smaller regulator to support the output volt-
age. However, if the LTC1873 is powered back up in
continuous mode, it will begin a soft-start cycle with a low
duty cycle, pulling the output down and corrupting the
data stored in SRAM. The solution is to tie FCB high,
allowing the device to start in discontinuous mode. Any
reverse current flow in QB will trip the discontinuous mode
circuitry, preventing the LTC1873 from pulling down the
output.
OVERVOLTAGE FAULT
The LTC1873 includes a single overvoltage fault flag for
both channels: FAULT. FAULT is an open-drain output
with an internal 10
μ
A pull-up. If either FB pin rises more
than 15% above the nominal 800mV value for more than
25
μ
s, the overvoltage comparator will trip, setting an
internal latch. This latch releases the pull-down at FAULT,
allowing the 10
μ
A pull-up to take it high. When FAULT
goes high, the LTC1873 stops all switching, turns both QB
(bottom synchronous) MOSFETs on continuously and
remains in this state until both RUN/SS pins are pulled low
simultaneously, the power supply is recycled, or the
FAULT pin is pulled low externally. This behavior is
intended to protect a potentially expensive load from
overvoltage damage at all costs. Under some conditions,
this behavior can cause the output voltage to undershoot
below ground. If latched FAULT mode is used, a Schottky
diode should be added with its cathode at the output and
its anode at ground to clamp the negative voltage to a safe
level and prevent possible damage to the load and the
output capacitors.
Note that in overvoltage conditions, the MAX comparator
will kick in at just +5%, turning QB on continuously long
before the output reaches +15%. Under most fault condi-
tions, this is adequate to bring the output back down
without firing the fault latch. Additionally, if MAX success-
fully keeps the output below +15%, the LTC1873 will
resume normal regulation as soon as the output overvolt-
age fault is resolved.
In some circuits, the OV latch can be a liability. Consider
a circuit where the output voltage at one channel may be
changed on the fly by changing the VID code or switching
in different feedback resistors. A downward adjustment
of greater than 15% will fire the fault latch, disabling both
sides of the LTC1873 until the power is recycled. In
circuits such as this, the fault latch can be disabled by
grounding the FAULT pin. The internal latch will still be set
the first time the output exceeds +15%, but the 10
μ
A
current source pull-up will not be able to pull FAULT high,
and the LTC1873 will ignore the latch and continue
APPLICATIOU
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| LTC1873EG#PBF | 功能描述:IC REG CTRLR BUCK PWM VM 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC1873EG#TR | 功能描述:IC REG CTRLR BUCK PWM VM 28-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC1873EG#TRPBF | 功能描述:IC REG CTRLR BUCK PWM VM 28-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:4,500 系列:PowerWise® PWM 型:控制器 輸出數(shù):1 頻率 - 最大:1MHz 占空比:95% 電源電壓:2.8 V ~ 5.5 V 降壓:是 升壓:無 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:6-WDFN 裸露焊盤 包裝:帶卷 (TR) 配用:LM1771EVAL-ND - BOARD EVALUATION LM1771 其它名稱:LM1771SSDX |
| LTC1874EGN | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:否 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
| LTC1874EGN#PBF | 功能描述:IC REG CTRLR BUCK PWM CM 16-SSOP RoHS:是 類別:集成電路 (IC) >> PMIC - 穩(wěn)壓器 - DC DC 切換控制器 系列:- 標準包裝:2,500 系列:- PWM 型:電流模式 輸出數(shù):1 頻率 - 最大:500kHz 占空比:96% 電源電壓:4 V ~ 36 V 降壓:無 升壓:是 回掃:無 反相:無 倍增器:無 除法器:無 Cuk:無 隔離:無 工作溫度:-40°C ~ 125°C 封裝/外殼:24-WQFN 裸露焊盤 包裝:帶卷 (TR) |
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