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參數(shù)資料
| 型號： | LRS1341 |
| 廠商： | Sharp Corporation |
| 英文描述： | Stacked Chip 16M Flash Memory and 2M SRAM |
| 中文描述： | 堆疊芯片1,600快閃記憶體以及2M SRAM |
| 文件頁數(shù)： | 22/24頁 |
| 文件大?。?/td> | 197K |
| 代理商： | LRS1341 |
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
22
Data Sheet
GENERAL DESIGN GUIDELINES
Supply Power
Maximum difference (between F-V
CC
and S-V
CC
) of
the voltage is less than 0.3 V.
Power Supply and Chip Enable of Flash
Memory and SRAM
S-CE
1
should not be LOW and S-CE
2
should not be
HIGH when F-CE is LOW simultaneously.
If the two memories are active together, they may
not operate normally because of interference noises or
data collision on DQ bus.
Both F-V
CC
and S-V
CC
need to be applied by the
recommended supply voltage at the same time except
SRAM data retention mode.
Power Up Sequence
When turning on Flash memory power supply, keep
F-RP LOW. After F-V
CC
reaches over 2.7 V, keep F-RP
LOW for more than 100 ns.
Device Decoupling
The power supply needs to be designed carefully
because one of the SRAM and the Flash Memory is in
standby mode when the other is active. A careful
decoupling of power supplies is necessary between
SRAM and Flash Memory. Note peak current caused
by transition of control signals (F-CE, S-CE
1
, S-CE
2
).
FLASH MEMORY DATA PROTECTION
Noises having a level exceeding the limit specified in
the specification may be generated under specific
operating conditions on some systems.
Such noises, when induced onto F-WE signal or
power supply may be interpreted as false commands,
causing undesired memory updating.
To protect the data stored in the flash memory
against unwanted overwriting, systems operating with
the flash memory should have the following write pro-
tect designs, as appropriate:
Protecting Data in Specific Block
By setting a F-WP to LOW, only the boot block can
be protected against overwriting. Parameter and main
blocks cannot be locked. System program, etc., can be
locked by storing them in the boot block. When a high
voltage is applied to F-RP, overwrite operation is
enabled for all blocks.
For further information on setting/resetting of block
bit, and controlling of F-WP and F-RP, refer to the
‘
Command Definitions
’
section.
Data Protection Through F-V
PP
When the level of F-V
PP
is lower than F-V
PPLK
(lock-
out voltage), write operation on the flash memory is dis-
abled. All blocks are locked and the data in the blocks
are completely write protected.
For the lockout voltage refer to the
‘
DC Characteris-
tics
’
section.
Data Protection During Voltage Transition
DATA PROTECTION THROUGH F-RP
When the F-RP is kept LOW during power up and
power down sequence, write operation on the flash
memory is disabled, write protecting all blocks.
For details of F-RP control refer to the
‘
Flash
Memory AC Electrical Characteristics
’
section.
DESIGN CONSIDERATIONS
Power Supply Decoupling
To avoid a bad effect on the system by flash memory
power switching characteristics, each device should
have a 0.1 μF ceramic capacitor connected between its
V
CC
and GND and between its V
PP
and GND. LOW
inductance capacitors should be placed as close as
possible to package leads.
V
PP
Trace on Printed Circuit Boards
Updating the memory contents of flash memories
that reside in the target system requires that the printed
circuit board designer pay attention to the V
PP
Power
Supply trace. Use similar trace widths and layout con-
siderations given to the V
CC
power bus.
The Inhibition of Overwrite Operation
Please do not execute reprogramming
‘
0
’
for the bit
which has already been programmed
‘
0
’
. Overwrite
operation may generate unerasable bit. In case of
reprogramming
‘
0
’
to the data which has been pro-
grammed
‘
1
’
.
Program
‘
0
’
for the bit in which you want to change
data from
‘
1
’
to
‘
0
’
.
Program
‘
1
’
for the bit which has already been pro-
grammed
‘
0
’
.
For
example,
changing
‘
1011110110111101
’
to
‘
1010110110111100
’
requires
‘
1110111111111110
’
programming.
data
from
Power Supply
Block erase, full chip erase, word write and lock-bit
configuration with an invalid V
PP
(see
‘
DC Characteris-
tics
’
) produce spurious results and should not be
attempted. Device operations at invalid V
CC
voltage
product spurious results and should be attempted.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| LRS1348 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Flash ROM |
| LRS1360C | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MIXED MEMORY|SRAM+EEPROM|HYBRID|BGA|72PIN|PLASTIC |
| LRS1361B | 制造商:Sharp Microelectronics 功能描述:QUOTE B04419SC |
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