![](http://datasheet.mmic.net.cn/220000/LRS1341_datasheet_15488684/LRS1341_16.png)
LRS1341/LRS1342
Stacked Chip (16M Flash & 2M SRAM)
16
Data Sheet
SRAM AC ELECTRICAL CHARACTERISTICS
AC Test Conditions
NOTE:
*Including scope and jig capacitance.
Read Cycle
T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V
NOTE:
*Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
Write Cycle
T
A
= -25
°
C to +85
°
C, V
CC
= 2.7 V to 3.6 V
NOTE:
*Active output to HIGH impedance and HIGH impedance to output active
tests specified for a ±200 mV transition from steady state levels into the test load.
PARAMETER
CONDITION
Input Pulse Level
Input Rise and Fall Time
Input and Output Timing Reference Level
Output Load*
0.4 V to 2.7 V
5 ns
1.5 V
1TTL + C
L
(30 pF)
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Read Cycle Time
Address Access Time
t
RC
t
AA
t
ACE1
t
ACE2
t
BE
t
OE
t
OH
t
LZ1
t
LZ2
t
OLZ
t
BLZ
t
HZ1
t
HZ2
t
OHZ
t
BHZ
85
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
85
85
85
85
45
Chip Enable Access Time
S-CE
1
S-CE
2
Byte Enable Access Time
Output Enable to Output Valid
Output hold from address change
10
10
10
10
10
0
0
0
0
S-CE
1
, S-CE
2
LOW to Output Active*
S-CE
1
S-CE
2
S-OE LOW to Output Active*
S-UB or S-LB LOW to Output in HIGH Impedance*
S-CE
1
, S-CE
2
HIGH to Output in HIGH Impedance*
S-CE
1
S-CE
2
25
25
25
25
S-OE HIGH to Output in HIGH Impedance*
S-UB or S-LB HIGH to Output in HIGH Impedance*
PARAMETER
SYMBOL
MIN.
MAX.
UNIT
Write Cycle Time
Chip Enable to End of Write
Address Valid to End of Write
Byte Enable to End of Write
Address Setup Time
Write Pulse Width
Write Recovery Time
Input Data Setup Time
Input Data Hold Time
S-WE HIGH to Output Active*
S-WE LOW to Output in HIGH Impedance*
t
WC
t
CW
t
AW
t
BW
t
AS
t
WP
t
WR
t
DW
t
DH
t
OW
t
WZ
85
75
75
75
0
65
0
35
0
5
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
25