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參數(shù)資料
| 型號(hào)： | LP1072 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 802.11a/b/g Baseband System Solution |
| 中文描述： | 802.11a/b/g無線基帶系統(tǒng)解決方案 |
| 文件頁數(shù)： | 6/32頁 |
| 文件大小： | 293K |
| 代理商： | LP1072 |
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LP1072 Advance Information, Rev. 0.3
6
Freescale Semiconductor
PRELIMINARY
Functional Description
3.1.8
SDIO Registers
TBA
3.1.9
Clock Control
TBA
3.1.10
Clock Gating
This block contains all the control logic required to gate individual sub-block clocks.
3.2
Media Access Control (MAC) Subsystem
3.2.1
Protocol Accelerator Subsystem (PAS)
The main function of the Protocol Accelerator Subsystem is to provide hardware acceleration functions
for the MAC Software to perform the time critical aspects of the 802.11 protocol.
The PAS contains the following:
Shared Memory Controller – provided arbitrated access to the shared memory (MAC memory)
WEP Hardware Engine
AES Hardware Engine
802.11 Protocol Accelerator – for support of time-critical MAC functions
Generic Host Interface
3.2.2
AES Block
The contents of the AES block are:
AES encryption/decryption core that performs AES encryption/decryption of a 128bit block.
Offset Codebook (OCB) mode encipher/decipher wrapper that performs OCB mode key
generation for the AES core.
DMA controller and Shared Memory Interface that controls the reading/writing of data blocks
from/to the PAS shared memory controller.
Control Registers, used to configure the operation of the AES block.
3.2.3
WEP Block
TBA
3.3
PHY Subsystem
TBA
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