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參數(shù)資料
| 型號： | LP1072 |
| 廠商： | 飛思卡爾半導(dǎo)體(中國)有限公司 |
| 英文描述： | 802.11a/b/g Baseband System Solution |
| 中文描述： | 802.11a/b/g無線基帶系統(tǒng)解決方案 |
| 文件頁數(shù)： | 5/32頁 |
| 文件大?。?/td> | 293K |
| 代理商： | LP1072 |
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Functional Description
LP1072 Advance Information, Rev. 0.3
Freescale Semiconductor
5
PRELIMINARY
3.1.1
UART
The UART is used for testing and diagnostic purposes and is capable of supporting data transfer rates of
up to 115.2 kbps.
3.1.2
JTAG
TBA
3.1.3
Serial EEPROM Interface
The LP1072 supports an external serial EEPROM for storing the boot loader, MAC address, calibration
data and any other vendor-specific data. The LP1072 supports serial EEPROMs of sizes from 8 Kbit
(organized as 1024 entries of 8 bits each, or 1024 x 8) up to 512 Kbit (organized as 65,536 x 8). Serial
EEPROMs from the following vendors have been tested and verified to work with the LP1072:
ATMEL (
http:/www.atmel.com
)
ST Microelectronics (
http://www.st.com
)
Microchip Technology (
http://www.microchip.com
)
Catalyst Semiconductor (
http://www.catsemi.com
)
Integrated Silicon Solutions, Inc. (
http://www.issi.com
)
The EEPROM is supported through GPIOs. There is no dedicated hardware to support either I
2
C or SPI
serial EEPROMs.
The operating frequency of the serial EEPROM port is 400 kHz with a supply voltage of 3.0 V.
3.1.4
GPIO
To support vendor-specific needs, the LP1072 provides eight bi-directional General Purpose Input Output
(GPIO) pins. Each pin can be independently configured as an input, output or an interrupt source. On reset,
the GPIOs default as inputs, i.e. output drivers enables will be inactive.
3.1.5
RMB Registers
This block contains all the reset logic for both CPUs contained in the BRC and chip-wide reset control. It
also defines controls for memory address re-mapping.
3.1.6
Watchdog
TBA
3.1.7
Interrupt Controller
TBA
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