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參數(shù)資料
| 型號： | LP1072 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | 802.11a/b/g Baseband System Solution |
| 中文描述： | 802.11a/b/g無線基帶系統(tǒng)解決方案 |
| 文件頁數(shù)： | 12/32頁 |
| 文件大?。?/td> | 293K |
| 代理商： | LP1072 |
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LP1072 Advance Information, Rev. 0.3
12
Freescale Semiconductor
PRELIMINARY
LP1072 Interfaces
Table 8. SDIO Function 1 Registers
Bit
Name
Description
ARM
Access
HOST
Access
Reset
Watchdog Status Register (offset 0x000E)
0
Wdog_reset
This is a read only bit that when ‘1’ indicates that
the LP1072 ASIC has had a watchdog reset
occur.
R
R
0
7:1
Reserved
—
—
—
—
SDIO Host to Device Interrupt request register 0 (0x000F)
7:0
Write_sdio_arm_int
Each bit in this register is 1 of 8 ARM interrupt
requests from the SDIO Host to the device ARM.
The Host should request an interrupt by writing a
“1” to the corresponding bit in this register. The
register will be read as a “1” until the ARM clears
the register. Once the ARM has cleared the
register then the corresponding bit will be read as
“0” again.
—
RW
0’s
Device to SDIO Host Interrupt Source register 0 (0x0013)
7:0
Arm_to_sdio_int_clr[7:0] for
writes.
Arm_to_sdio_int_src[7:0] for
reads.
This register contains the interrupt pending status
of the SDIO Host interrupt from the device. The
device is capable of generating up to 8 individual
requests. Each bit in this register is ANDed with
the corresponding ARM to SDIO Host Interrupt
enable register. The ANDed bits are then ORed
together to generate a single SDIO Host interrupt
in the cccr register space. To clear a particular
interrupt bit the SDIO Host should write a “1” to
that particular bit in this register.
—
RW
0’s
Device to SDIO Host Interrupt Source register 1 (0x0014)
2:0
Arm_to_sdio_int_clr[10:8] for
writes.
Arm_to_sdio_int_src[10:8]
for reads.
This register contains the interrupt pending status
of the SDIO Host semaphore 0-2 host granted
indication. When the Host requests a semaphore
the corresponding interrupt will be triggered when
the host has been granted the interrupt. Bit 0 is
semaphore 0; bit 1 is semaphore 1; and bit 2 is
semaphore 2. Each bit in this register is ANDed
with the corresponding ARM to SDIO Host
Interrupt enable register. The ANDed bits are then
ORed together to generate a single SDIO Host
interrupt in the cccr register space. To clear a
particular interrupt bit the SDIO Host should write
a “1” to that particular bit in this register.
-
RW
0’s
7:3
Reserved
—
-
-
-
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