參數(shù)資料
型號： LMK04002BEVAL
廠商： National Semiconductor
文件頁數(shù)： 9/65頁
文件大?。?/td> 0K
描述： BOARD EVAL PRECISION CLOCK PLL
標準包裝： 1
系列： PowerWise®
主要目的： 計時，時鐘調(diào)節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04002
主要屬性： 122.88 MHz VCXO
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
LMK040x0 (34)
BW = 12 kHz to 20 MHz
195
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
230
Integrated RMS Jitter
LMK040x1 (35)
BW = 12 kHz to 20 MHz
195
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
220
Integrated RMS Jitter
JCLKout
fs
LVCMOS
LMK040x2 (36)
BW = 12 kHz to 20 MHz
195
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
230
Integrated RMS Jitter
LMK040x3 (37)
BW = 12 kHz to 20 MHz
240
fCLKout = 245.76 MHz
BW = 100 Hz to 20 MHz
260
Integrated RMS Jitter
Digital Inputs (CLKuWire, DATAuWire, LEuWire)
VIH
High-Level Input Voltage
1.6
VCC
V
VIL
Low-Level Input Voltage
0.4
V
IIH
High-Level Input Current
VIH = VCC
-5
25
A
IIL
Low-Level Input Current
VIL = 0
-5.0
5.0
A
Digital Inputs (GOE, SYNC*)
VIH
High-Level Input Voltage
1.6
VCC
V
VIL
Low-Level Input Voltage
0.4
V
IIH
High-Level Input Current
VIH = VCC
-5.0
5.0
A
IIL
Low-Level Input Current
VIL = 0
-40.0
5.0
A
Digital Outputs (CLKinX_LOS, LD)
VOH
High-Level Output Voltage
IOH = -500 A
VCC - 0.4
V
VOL
Low-Level Output Voltage
IOL = 500 A
0.4
V
Default Power On Reset Clock Output Frequency
CLKout2, LM040x0
50
CLKout2, LM040x1
62
Default output clock frequency
fCLKout-startup
MHz
at device power on
CLKout2, LM040x2
68
CLKout2, LM040x3
81
LVDS Clock Outputs (CLKoutX)
Maximum Frequency
fCLKout
RL = 100 Ω
1080
MHz
(38)
CLKoutX to CLKoutY
LVDS-LVDS, T = 25 °C,
TSKEW
30
ps
(39)
FCLK = 800 MHz, RL= 100 Ω
VOD
Differential Output Voltage
250
350
450
mV
Change in Magnitude of VOD
R = 100
Ω differential
ΔVOD
for complementary output
-50
50
mV
termination, AC coupled to
states
receiver input,
FCLK = 800 MHz,
VOS
Output Offset Voltage
1.125
1.25
1.375
V
T = 25 °C
Change in VOS for
ΔVOS
35
|mV|
complementary output states
ISA
Output short circuit current -
Single-ended output shorted to
-24
24
mA
ISB
single ended
GND, T = 25 °C
Output short circuit current -
Complimentary outputs tied
ISAB
-12
12
mA
differential
together
LVPECL Clock Outputs (CLKoutX) (40)
(38) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to of a period, or, 0.5/FCLKoutX.
(39) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for
delay mode.
(40) LVPECL/2VPECL is programmable for all NSIDs.
Copyright 2008–2011, Texas Instruments Incorporated
17
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
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LMK04002BISQ 制造商:NSC 制造商全稱:National Semiconductor 功能描述:Low-Noise Clock Jitter Cleaner with Cascaded PLLs
LMK04002BISQ/NOPB 功能描述:時鐘合成器/抖動清除器 RoHS:否 制造商:Skyworks Solutions, Inc. 輸出端數(shù)量: 輸出電平: 最大輸出頻率: 輸入電平: 最大輸入頻率:6.1 GHz 電源電壓-最大:3.3 V 電源電壓-最小:2.7 V 封裝 / 箱體:TSSOP-28 封裝:Reel
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