參數(shù)資料
型號： LMK04002BEVAL
廠商： National Semiconductor
文件頁數(shù)： 10/65頁
文件大?。?/td> 0K
描述： BOARD EVAL PRECISION CLOCK PLL
標(biāo)準(zhǔn)包裝： 1
系列： PowerWise®
主要目的： 計(jì)時，時鐘調(diào)節(jié)器
嵌入式： 否
已用 IC / 零件： LMK04002
主要屬性： 122.88 MHz VCXO
次要屬性： 集成式 PLL 和 VCO
已供物品： 板，線纜
產(chǎn)品目錄頁面： 1275 (CN2011-ZH PDF)
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Electrical Characteristics (continued)
(3.15 V
≤ VCC ≤ 3.45 V, -40 °C ≤ TA ≤ 85 °C. Typical values represent most likely parametric norms at VCC = 3.3 V, TA = 25
°C, at the Recommended Operating Conditions at the time of product characterization and are not guaranteed.)
Symbol
Parameter
Conditions
Min
Typ
Max
Units
Maximum Frequency
fCLKout
1080
MHz
(41)
LVPECL-to-LVPECL,
CLKoutX to CLKoutY
T = 25 °C, FCLK = 800 MHz,
TSKEW
40
ps
(42)
each output terminated with
120
Ω to GND.
VCC -
VOH
Output High Voltage
V
0.93
FCLK = 100 MHz, T = 25 °C
Termination = 50
Ω to
VCC -
VOL
Output Low Voltage
V
VCC - 2 V
1.82
VOD
Output Voltage
660
890
965
mV
2VPECL Clock Outputs (CLKoutX)
Maximum Frequency
fCLKout
1080
MHz
(41)
2VPECL-2VPECL, T=25 °C,
CLKoutX to CLKoutY
TSKEW
FCLK = 800 MHz, each output
40
ps
(42)
terminated with 120
Ω to GND.
VCC -
VOH
Output High Voltage
V
0.95
FCLK = 100 MHz, T = 25 °C
Termination = 50
Ω to
VCC -
VOL
Output Low Voltage
V
VCC - 2 V
1.98
VOD
Output Voltage
800
1030
1200
mV
LVCMOS Clock Outputs (CLKoutX)
fCLKout
Maximum Frequency
5 pF Load
250
MHz
VOH
Output High Voltage
1 mA Load
VCC - 0.1
V
VOL
Output Low Voltage
1 mA Load
0.1
V
IOH
Output High Current (Source)
VCC = 3.3 V, VO = 1.65 V
28
mA
IOL
Output Low Current (Sink)
VCC = 3.3 V, VO = 1.65 V
28
mA
Skew between any two
RL = 50 Ω, CL = 10 pF,
TSKEW
LVCMOS outputs, same
T = 25 °C, FCLK = 100 MHz.
100
ps
channel or different channel
(43)
VCC/2 to VCC/2, FCLK = 100
DUTYCLK
Output Duty Cycle
45
50
55
%
MHz, T = 25 °C (44)
20% to 80%, RL = 50
Ω,
TR
Output Rise Time
400
ps
CL = 5 pF
80% to 20%, RL = 50
Ω,
TF
Output Fall Time
400
ps
CL = 5 pF
Mixed Clock Skew
Same device, T = 25 °C,
LVPECL to LVDS skew
-230
ps
250 MHz
Same device, T = 25 °C,
TSKEW ChanX - ChanY
LVDS to LVCMOS skew
770
ps
250 MHz
Same device, T = 25 °C,
LVCMOS to LVPECL skew
-540
ps
250 MHz
Microwire Interface Timing
TCS
Data to Clock Set Up Time
See Microwire Input Timing
25
ns
TCH
Data to Clock Hold Time
See Microwire Input Timing
8
ns
(41) For Clock output frequencies > 1 GHz, the maximum allowable clock delay is limited to of a period, or, 0.5/FCLKoutX.
(42) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for
delay mode.
(43) Equal loading and identical channel configuration on each channel is required for specification to be valid. Specification not valid for
delay mode.
(44) Guaranteed by characterization.
18
Copyright 2008–2011, Texas Instruments Incorporated
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