參數(shù)資料
型號(hào): LMK04002BEVAL
廠商: National Semiconductor
文件頁(yè)數(shù): 40/65頁(yè)
文件大?。?/td> 0K
描述: BOARD EVAL PRECISION CLOCK PLL
標(biāo)準(zhǔn)包裝: 1
系列: PowerWise®
主要目的: 計(jì)時(shí),時(shí)鐘調(diào)節(jié)器
嵌入式:
已用 IC / 零件: LMK04002
主要屬性: 122.88 MHz VCXO
次要屬性: 集成式 PLL 和 VCO
已供物品: 板,線纜
產(chǎn)品目錄頁(yè)面: 1275 (CN2011-ZH PDF)
C2
PLL2
Phase
Detector
R2
C1
C3
C4
R3
R4
LMK040xx
PLL2 Internal Loop Filter
PLL2 External Loop
Filter
C2
PLL1
Phase
Detector
R2
CPout1
C1
LMK040xx
PLL1 External Loop
Filter
C
Po
u
t2
External VCXO
Internal VCO
SNOSAZ8J – SEPTEMBER 2008 – REVISED SEPTEMBER 2011
Figure 14. Loop Filter
Table 33. Typical Current Consumption for Selected Functional Blocks
Power
Typical ICC
Power
Dissipated in
(Temp = 25 °C,
Dissipated in
LVPECL/2VPECL
Block
Condition
VCC = 3.3 V)
device
Emitter
(mA)
(mW)
Resistors
(mW)
Single input clock (CLKIN_SEL = 0 or 1); LOS disabled;
Entire device,
PLL1 and PLL2 locked; All CLKouts are off; No LVPECL
115
380
-
core current
emitter resistors connected
REFMUX
Enable auto-switch mode (CLKIN_SEL = 2 or 3)
4.3
14
-
LOS
Enable LOS (LOS_TYPE = 1, or 2, or 3)
3.6
12
-
Low Channel
The low channel internal buffer is enabled when CLKout0 is
10
33
-
Internal Buffer
enabled
High Channel
The high channel internal buffer is enabled when one of
10
33
-
Internal Buffer
CLKout1 through CLKout4 is enabled
Divider bypassed (CLKout_MUX = 0, 2)
0
-
Divide circuitry
Divider enabled, divide = 2 (CLKout_MUX = 1, 3)
5.3
17
-
per output
Divider enabled, divide > 2 (CLKout_MUX = 1, 3)
8.5
28
-
Delay bypassed (CLKout_MUX = 0, 1)
0
-
Delay circuitry per
Delay enabled, delay < 8 (CLKout_MUX = 2, 3)
5.8
19
-
output
Delay enabled, delay > 7 (CLKout_MUX = 2, 3)
9.9
33
-
Fout Buffer
EN_Fout = 1
14.5
48
-
LVDS Buffer
LVDS buffer, enabled
19.3
64
-
Copyright 2008–2011, Texas Instruments Incorporated
45
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