參數(shù)資料
型號(hào)： LM1253AN
廠商： NATIONAL SEMICONDUCTOR CORP
元件分類： 畫(huà)面疊加
英文描述： Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator
中文描述： ON-SCREEN DISPLAY IC, PDIP28
封裝： 0.600 INCH, PLASTIC, DIP-28
文件頁(yè)數(shù)： 43/57頁(yè)
文件大?。?/td> 1621K
代理商： LM1253AN
Control Register Definitions
(Continued)
Display Window 2 Horizontal Pixel Start Location Register (I
2
C address 8418h).
REGISTER NAME: HSTRT2 (8418h)
Bit 7
Bit 0
2H7
2H6
2H5
2H4
2H3
2H2
2H1
2H0
Bits 7–0: Display Window 2 Horizontal Pixel Start Location. These seven bits determine the starting horizontal pixel location,
which is determined by multiplying the value of these bits by 4 and adding 30 pixels. Due to pipeline delays, the first
usable location for the OSD window is approx 42 pixels to the right of the horizontal flyback pulse. For this reason, the
display start location must be programmed with a number larger than 2, otherwise improper operation may occur.
This byte must be set so the entire OSD window is within the active video.
Display Window 2 Vertical Pixel Start Location Register (I
2
C address 8419h).
REGISTER NAME: VSTRT2 (8419h)
Bit 7
Bit 0
2V7
2V6
2V5
2V4
2V3
2V2
2V1
2V0
Bits 7–0: Display Window 2 Vertical Pixel Start Location. These eight bits determine the starting vertical pixel location in con-
stant height character lines, which is determined by multiplying the value of these bits by 2. (Note, each character line
is treated as a single auto-height character pixel line, so multiple scan lines may actually be displayed in order to main-
tain accurate position relative to the character cell size—see Constant Character Height Mechanism section).
This byte must be set so the entire OSD window is within the active video.
Display Window 2 Starting Address in the Display Page RAM (I
2
C address 841Ah–841Bh).
REGISTER NAME: W2STRTADRH (841Bh) W2STRTADRL (841Ah)
Bit 15
Bit 8
Bit 7
Bit 0
RSV
RSV
RSV
RSV
RSV
RSV
RSV
2ad8
2ad7
2ad6
2ad5
2ad4
2ad3
2ad2
2ad1
2ad0
Bits 8–0: Display Window 2’s Starting Address in the Display Page RAM. This register determines the starting address of Dis-
play Window 2 in the Display Page RAM. This first address location will always contain the SL code for the first row
of Display Window 2.
Bits 7–5: RESERVED.
Display Window 2 Column Width Control Register (I
2
C address 841Ch–841Fh).
REGISTER NAME: COLWIDTH2B3 (841Fh) COLWIDTH2B2 (841Eh) COLWIDTH2B1 (841Dh) COLWIDTH2B0 (841Ch)
Bit 31
Bit 24
Bit 23
Bit 16
COL31
COL30
COL29
COL28
COL27
COL26 COL25 COL24 COL23 COL22 COL21 COL20 COL19 COL18 COL17 COL16
Bit 15
Bit 8
Bit 7
Bit 0
COL15
COL14
COL13
COL12
COL11
COL10
COL9
COL8
COL7
COL6
COL5
COL4
COL3
COL2
COL1
COL0
Bits 31–0: Display Window 2 Column Width 2x Enable Bits. These thirty-two bits correspond to columns 31–0 of Display Win-
dow 2, respectively. A value of zero indicates the column will have normal width (12 pixels). A value of one indicates
the column will be twice as wide as normal (24 pixels). For the double wide case, each Character Font pixel location
will be displayed twice, in two consecutive horizontal pixel locations.
The user should note that if more than 32 display characters are programmed to reside on a row, then all display
characters after the first thirty-two will have normal width (12 pixels).
L
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