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參數(shù)資料
| 型號： | LM1253AN |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 畫面疊加 |
| 英文描述： | Monolithic Triple 180 MHz I2C CRT Pre-amp With Integrated Analog On Screen Display (OSD) Generator |
| 中文描述： | ON-SCREEN DISPLAY IC, PDIP28 |
| 封裝： | 0.600 INCH, PLASTIC, DIP-28 |
| 文件頁數(shù)： | 28/57頁 |
| 文件大?。?/td> | 1621K |
| 代理商： | LM1253AN |
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Micro-Controller Interface
(Continued)
The write sequence consists of the Start Pulse, the Slave
Device Address, the Read/Write bit (a zero, indicating a
write) and the Acknowledge bit; the next byte is the least sig-
nificant byte of the address to be accessed, followed by its
Acknowledge bit. This is then followed by a byte containing
the most significant address byte, followed by its Acknowl-
edge bit. Then a Stop bit indicates the end of the address
only write access.
Next the read data access will be performed beginning with
the Start Pulse, the Slave Device Address, the Read/Write
bit (a one, indicating a read) and the Acknowledge bit. The
next 8 bits will be the read data driven out by the LM1253A
pre-amp associated with the address indicated by the two
address bytes. Subsequent read data bytes will correspond
to the next increment address locations.
Read data from the LM1253A only when both OSD windows
are disabled.
DS101265-46
FIGURE 40. I
2
C Read Sequence
L
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