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參數(shù)資料
| 型號(hào)： | LM1236 |
| 廠商： | National Semiconductor Corporation |
| 英文描述： | 150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD ROM, 512 Character RAM and 4 DACs |
| 中文描述： | 150 MHz的I2C兼容的RGB前置放大器254字符OSD光盤，512個(gè)字符RAM和4 DAC的內(nèi)置 |
| 文件頁數(shù)： | 38/43頁 |
| 文件大?。?/td> | 1898K |
| 代理商： | LM1236 |
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Pre-Amplifier Interface Registers
(Continued)
Bit 5
When this bit is a 0, the full-scale outputs of DACs 1–3 are 0.5V to 4.5V. When it is a 1, the
full-scale level is 0.5V to 2.5V.
When this bit is a 0, the DAC 4 output is independent. When it is a 1, the DAC 4 output is scaled
by 50% and added to the outputs of DACs 1–3.
Reserved and should be set to zero.
Bit 6
Bit 7
Global Video Control:
GLOBALCTRL (0x8439)
Bank
X
Power
PS
Blank
BV
X
X
X
X
X
Bit 0
When this bit is a 1, the video outputs are blanked (set to black level). When it is a 0, video is not
blanked.
When this bit is a 1, the analog sections of the preamplifier are shut down for low power
consumption. When it is a 0, the analog sections are enabled.
Reserved.
Bit 1
Bits 7–3
Auxiliary Control:
AUXCTRL (0x843A)
Reserved
X
Horizontal Blank Position
HBPOS[30]
H. Blank
HBPOS_EN
Reserved
X
H Blnk
HBD
Bit 0
When this bit is a 0, the horizontal blanking input at pin 24 is gated to the video outputs to provide
horizontal blanking. When it is a 1, the horizontal blanking at the outputs is disabled.
Reserved
When this bit is a 1, the position of the Horizontal Blanking pulse can be programmably varied
relative to the horizontal flyback in number of pixels. When this bit is a 0, which is by default, the
horizontal blanking pulse position will not be programmable.
These 4 bits determine the position of the Horizontal Blanking Pulse with respect to the horizontal
flyback in number of pixels.
Reserved
Bit 1
Bit 2
Bits 6–3
Bit 7
PLL Range:
PLLFREQRNG (0x843E)
Res’d
PLL
Auto Mode
PLL_AUTO
Clamp
Res’d
OSD
VBlank
PLL
Pre-calibration
PFR[1:0]
X
CLMP
X
OOR
VBL
Bits 1–0
Bit 2
These bits must be set to 0 to pre-calibrate the PLL Auto feature.
This is the Vertical Blanking register. When this bit is a 1, vertical blanking is gated to the video outputs. When
set to a 0, the video outputs do not have vertical blanking.
This is the OSD override bit. This should be set to 0 for normal operation. When set to a 1, the video outputs
are disconnected and OSD only is displayed. This is useful for the OSD display of special conditions such as
“No Signal” and “Input Signal Out of Range”, to avoid seeing unsynchronized video.
Reserved and should be set to zero.
This is the Clamp Polarity bit. When set to a 0, the LM1236 expects a positive going clamp pulse. When set to
a 1, the expected pulse is negative going.
When this bit is set, the PLL Auto Mode will automatically determine the optimum frequency range of the
Phase Locked Loop.
Reserved and should be set to zero.
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
L
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LM1236AAA/NA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD ROM, 512 Character RAM and 4 DACs |
| LM1237 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD and 4 DACs |
| LM1237_04 | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD and 4 DACs |
| LM1237AAF/NA | 制造商:NSC 制造商全稱:National Semiconductor 功能描述:150 MHz I2C Compatible RGB Preamplifier with Internal 254 Character OSD and 4 DACs |
| LM1237BAAF/NA | 功能描述:IC PREAMP CMOS 150MHZ 24-DIP RoHS:是 類別:集成電路 (IC) >> 線性 - 視頻處理 系列:- 產(chǎn)品變化通告:Product Discontinuation 07/Mar/2011 標(biāo)準(zhǔn)包裝:3,000 系列:OMNITUNE™ 類型:調(diào)諧器 應(yīng)用:移動(dòng)電話，手機(jī)，視頻顯示器 安裝類型:表面貼裝 封裝/外殼:65-WFBGA 供應(yīng)商設(shè)備封裝:PG-WFSGA-65 包裝:帶卷 (TR) 其它名稱:SP000365064 |
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