參數(shù)資料
型號: LH79533
英文描述: ARM RISC CORE ASSPs ARM7TDMI
中文描述: ARM的RISC核心專用標準的ARM7TDMI
文件頁數(shù): 4/39頁
文件大?。?/td> 296K
代理商: LH79533
LH79520
System-on-Chip
4
8/21/02
Preliminary Data Sheet
SIGNAL DESCRIPTIONS
Table 1. LH79520 Signal Descriptions
PIN NO.
SIGNAL NAME
TYPE
DESCRIPTION
NOTES
MEMORY INTERFACE (MI)
2-7
9-12
14-17
19-22
24-27
29-32
50-54
56-63
65-66
67-69
71-74
76-79
81-84
86-87
101
109
110
111
112
102
104
105
107
108
106
41
42
43
44
46
47
48
38
34
35
36
37
39
144
A[25:0]
Output
Address Signals
D[31:0]
Input/Output
Data Input/Output Signals
1
SDCLK
DQM3
DQM2
DQM1
DQM0
SDCKE
nDCS1
nDCS0
nRAS
nCAS
nSDWE
nCS6
nCS5
nCS4
nCS3
nCS2
nCS1
nCS0
nOE
nBLE3
nBLE2
nBLE1
nBLE0
nWE
nWAIT
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Input
SDRAM Clock
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
Data Mask Output to SDRAMs
SDRAM Clock Enable
SDRAM Chip Select
SDRAM Chip Select
Row Address Strobe
Column Address Strobe
SDRAM Write Enable
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Chip Select
Static Memory Controller Output Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Byte Lane Enable / Byte Write Enable
Static Memory Controller Write Enable
Static Memory Controller External Wait Control
DMA CONTROLLER (DMAC)
DMA 0 End of Transfer
DMA 0 Acknowledge
DMA 0 Request
DMA 1 End of Transfer
DMA 1 Acknowledge
DMA 1 Request
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1, 3
148
147
146
157
145
144
DEOT0
nDACK0
DREQ0
DEOT1
DACK1
DREQ1
Output
Output
Input
Output
Output
Input
1
1
1
1
1
1, 3
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