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參數(shù)資料
| 型號： | LH79533 |
| 英文描述： | ARM RISC CORE ASSPs ARM7TDMI |
| 中文描述： | ARM的RISC核心專用標準的ARM7TDMI |
| 文件頁數(shù)： | 18/39頁 |
| 文件大?。?/td> | 296K |
| 代理商： | LH79533 |
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LH79520
System-on-Chip
18
8/21/02
Preliminary Data Sheet
VARIATIONS FROM THE 16C550 UART
The UART varies from the industry-standard
16C550 UART device in six ways:
Receive FIFO trigger levels are fixed at 8 bytes
Receive errors are stored in the FIFO, and do not
generate an interrupt.
The internal register map address space and each
register’s bit function differ.
The following 16C550 UART features are not sup-
ported:
1.5 stop bits (1 or 2 stop bits only are supported)
The forcing stick parity function
Independent receive clock.
Pulse Width Modulator (PWM)
Two independent output channels with separate
input clocks
Up to 16-bit resolution
Programmable synchronous mode support
– Allows external input to start PWM
Programmable pulse width (duty cycle), interval (fre-
quency), and polarity
– Static programming: PWM is stopped
– Dynamic programming: PWM is running
– Updates duty cycle, frequency, and polarity at the
end of a PWM cycle
– Wide programming range.
Vectored Interrupt Controller
The Vectored Interrupt Controller combines the
interrupt request signals from 20 internal and eight
external interrupt sources and applies them, after
masking and prioritization, to the IRQ and FIQ interrupt
inputs of the ARM7TDMI processor core.
The Interrupt Controller incorporates a hardware
interrupt vector logic with programmable priority for up
to 16 interrupt sources. This logic reduces the interrupt
response time for IRQ type interrupts compared to
solutions using software polling to determine the high-
est priority interrupt source. This significantly improves
the real-time capabilities of the LH79520 in embedded
control applications.
20 internal and eight external interrupt sources
– Individually maskable
– Status accessible for software polling
IRQ interrupt vector logic for up to 16 channels with
programmable priorities
All of the interrupt channels, with the exception of the
Watchdog Timer interrupt, can be programmed to
generate:
– FIQ interrupt request
– Non-vectored IRQ interrupt request (software to
poll IRQ source)
– Vectored IRQ interrupt request (up to 16 chan-
nels total)
The Watchdog timer can only generate FIQ interrupt
requests
External interrupt inputs programmable
– Edge triggered or level triggered
– Rising edge/active HIGH or falling edge/active
LOW
The 28 interrupt channels are shown in Table 4.
Table 4. Interrupt Channels
CHANNEL
INTERRUPT SOURCE
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
External Interrupt 0
External Interrupt 1
External Interrupt 2
External Interrupt 3
External Interrupt 4
External Interrupt 5
External Interrupt 6
External Interrupt 7
Spare Internal Interrupt 0
COMRX (used for debug)
COMTX (used for debug)
SSP RX time-out interrupt SSPRXTO
CLCD Combined Interrupt
SSP SSPTXINTR
SSP SSPRXINTR
SSP SSPRORINTR
SSP SSPINTR
Counter/Timer0
Counter/Timer1
Counter/Timer2
Counter/Timer3
UART ch0 Rx
UART ch0 Tx
UART ch0
UART ch1
UART ch2
DMA Combined
Unused
RTC_ALARM
WDT
27-29
30
31
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