參數(shù)資料
型號(hào)： LH79533
英文描述： ARM RISC CORE ASSPs ARM7TDMI
中文描述： ARM的RISC核心專(zhuān)用標(biāo)準(zhǔn)的ARM7TDMI
文件頁(yè)數(shù)： 23/39頁(yè)
文件大小： 296K
代理商： LH79533
System-on-Chip
LH79520
Preliminary Data Sheet
8/21/02
23
AC Specifications (Commercial)
All signals described in Table 6 relate to transi-
tions after a reference clock signal. The illustration in
Figure 7 represents all cases of these sets of mea-
surement parameters.
The reference clock signals in this design are:
HCLK, the System Bus clock
PCLK, the Peripheral Bus clock
SSPCLK, the Synchronous Serial Interface clock
UARTCLK, the UART Interface clock
LCDDCLK, the LCD Data clock from the
LCD Controller
and SDCLK, the SDRAM clock.
All signal transitions are measured from the 50%
point of the clock to the 50% point of the signal. See
Figure 7.
For outputs from the LH79520, tOVXXX (e.g. tOVA)
represents the amount of time for the output to become
valid from the rising edge of the reference clock signal.
Maximum requirements for tOVXXX are shown in
Table 6.
The signal tOHXXX (e.g. tOHA) represents the
amount of time the output will be held valid from the ris-
ing edge of the reference clock signal. Minimum
requirements for tOHXXX are listed in Table 6.
For Inputs, tISXXX (e.g. tISD) represents the
amount of time the input signal must be valid before the
rising edge of the clock signal. Minimum requirements
for tISXXX are shown in Table 6.
The signal tIHXXX (e.g. tIHD) represents the
amount of time the output must be held valid from the
rising edge of the reference clock signal. Minimum
requirements are shown in Table 6.
Figure 7. LH79520 Signal Timing
REFERENCE
CLOCK
OUTPUT
SIGNAL (O)
INPUT
SIGNAL (I)
tOVXXX
tOHXXX
tISXXX tIHXXX
79520-34
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