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參數(shù)資料
| 型號： | LH79533 |
| 英文描述： | ARM RISC CORE ASSPs ARM7TDMI |
| 中文描述： | ARM的RISC核心專用標準的ARM7TDMI |
| 文件頁數(shù)： | 27/39頁 |
| 文件大小： | 296K |
| 代理商： | LH79533 |
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System-on-Chip
LH79520
Preliminary Data Sheet
8/21/02
27
Static Memory Controller Waveforms
Figure 11 shows the waveform and timing for an
External Static Memory Write. Figure 12 shows the
waveform and timing for an External Static Memory
Read, with one Wait State. Figure 13 shows the wave-
form and timing for an External Static Memory Read,
with two Wait States.
The Static Memory Controller (SMC) supports an
nWAIT input that can be used by an external device to
extend the wait time during a memory access. The
SMC samples nWAIT at the beginning of at the begin-
ning of each system clock cycle. The system clock
cycle in which the nCSx signal is asserted counts as
the first wait state. See Figure 14. The SMC recognizes
that nWAIT is active within 2 clock cycles after it has
been asserted. To assure that the current access (read
or write) will be extended by nWAIT, at least two wait
states must be programmed for this bank of memory. If
N wait states are programmed, then the Static Memory
Controller (SMC) holds this state for N system clocks,
or until the SMC detects that nWAIT is inactive, which-
ever occurs last. As the number of wait states pro-
grammed increases, the amount of delay before
nWAIT must be asserted also increases. If only 2 wait
states are programmed, then nWAIT must be asserted
in the clock cycle immediately following the clock cycle
during which the nCSx signal is asserted. Once the
SMC detects that the external device has deactivated
nWAIT, the SMC will complete its access in 3 system
clock cycles.
The formula for the allowable delay between assert-
ing nCSx and asserting nWAIT is:
tASSERT = (system clock period) × (Wait States - 1)
(where Wait States is from 2 to 31.)
Figure 11. External Static Memory Write
HCLK
ADDRESS
DATA
A[25:0]
D[31:0]
nCSx
nBE[3:0], nWE
tOVA
tOVD
tOVD
tOHD
tOHCS
tOHBE, tOHWE
tOHA
tOVCS
tOVBE, tOVWE
79520-30
NOTE:
All signal transitions are measured from the
50% point of the clock to the 50% point of the signal.
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相關代理商/技術參數(shù) |
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|---|---|
| LH7A400 | 制造商:SHARP 制造商全稱:Sharp Electrionic Components 功能描述:32-Bit System-on-Chip |
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| LH7A400N0B000B3A | 功能描述:IC ARM9 BLUESTREAK MCU 256PBGA RoHS:否 類別:集成電路 (IC) >> 嵌入式 - 微控制器， 系列:BlueStreak ; LH7A 產品培訓模塊:The Ultra-Low Power MSP430 MSP430 Overview MSP430 Design Tools MSP430 Peripherals MSP430x2xx/4xx and Wireless Overview Portable Medical Solutions with MSP430 MSP430 for Utility Metering Solutions MSP430: How to JTAG MSP430, How To Use the Clock System Grace Software Graphical User Interface MCU Overview Driver Library MSP430Ware Overview 標準包裝:1 系列:MSP430x4xx 核心處理器:RISC 芯體尺寸:16-位 速度:8MHz 連通性:SPI，UART/USART 外圍設備:欠壓檢測/復位，LCD，POR，PWM，WDT 輸入/輸出數(shù):48 程序存儲器容量:32KB（32K x 8 + 256B） 程序存儲器類型:閃存 EEPROM 大小:- RAM 容量:1K x 8 電壓 - 電源 (Vcc/Vdd):1.8 V ~ 3.6 V 數(shù)據(jù)轉換器:A/D 8x12b 振蕩器型:內部 工作溫度:-40°C ~ 85°C 封裝/外殼:100-LQFP 包裝:Digi-Reel® 其它名稱:296-26232-6 |
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| LH7A400N0B000B5,551 | 制造商:NXP Semiconductors 功能描述: |
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