參數(shù)資料
型號(hào)： LH79533
英文描述： ARM RISC CORE ASSPs ARM7TDMI
中文描述： ARM的RISC核心專用標(biāo)準(zhǔn)的ARM7TDMI
文件頁(yè)數(shù)： 30/39頁(yè)
文件大小： 296K
代理商： LH79533
LH79520
System-on-Chip
30
8/21/02
Preliminary Data Sheet
SDRAM Memory Controller Waveforms
Figure 15 shows the waveform and timing for an
SDRAM Burst Read (page already open). Figure 16
shows the waveform and timing for SDRAM to Activate
a Bank and Write.
Figure 15. SDRAM Burst Read
Figure 16. SDRAM Bank Activate and Write
t
SDCLK
LH79520-35
A[15:0]
D[31:0]
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
5. SDCKE is HIGH.
SCLK
SDRAMcmd
t
OVXXX
t
OVB
t
OHXXX
READ
BANK,
COLUMN
tOVA
tISD tIHD
DATA n
DATA n + 1
DATA n + 2
DATA n + 3
79520-36
D[31:0]
SCLK
SDCKE
SDRAMcmd
tSDCLK
tOVC0
tOVXXX
tOVA
tOHXXX
tOVA
NOTES:
1. SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
2. tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
3. tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
4. nDQM is LOW.
ACTIVE
WRITE
DATA
BANK,
ROW
BANK,
COLUMN
tOVD
tOHD
A[15:0]
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