參數(shù)資料
型號： LH79533
英文描述： ARM RISC CORE ASSPs ARM7TDMI
中文描述： ARM的RISC核心專用標準的ARM7TDMI
文件頁數(shù)： 31/39頁
文件大?。?/td> 296K
代理商： LH79533
System-on-Chip
LH79520
Preliminary Data Sheet
8/21/02
31
External DMA Handshake Signal Timing
DREQ TIMING
Once asserted, DREQ0 or DREQ1 must not transi-
tion from LOW to HIGH again until after DACK0 or
nDACK1 has been asserted.
DACK/DEOT TIMING
These timing diagrams indicate when DACK0,
nDACK1, DEOT0 and DEOT1 occur in relation to an
external bus access to/from the external peripheral that
requested the DMA transfer.
The top diagram shows the timing with relation to a
single read or the last word of a burst read from the
requesting peripheral. The bottom diagram shows the
timing with relation to a single write or the last word of
a burst write to the requesting peripheral.
The timing of DACK/DEOT may become unpredict-
able when a Write to SDRAM occurs just prior to a sin-
gle word Write to the requesting peripheral. If the write
buffer is enabled for the SDRAM Controller, this can
cause the DACK/DEOT to occur an indeterminate
number of cycles prior to the actual Write to the
requesting peripheral.
Figure 17. DREQ Timing Restrictions
DREQ
MUST NOT
TRANSITON
DREQ MAY
TRANSITON
tDREQ0L,
tDREQ1L
DREQ0,
DREQ1
DACK0
nDACK1
NOTE:
tDREQ0L = DREQ0 LOW Pulse Width = 2 HCLK MIN.
tDREQ1L = DREQ1 LOW Pulse Width = 2 HCLK MIN.
79520-158
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