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參數(shù)資料
| 型號(hào)： | LH28F032SUTD-70 |
| 英文描述： | x8/x16 Flash EEPROM Module |
| 中文描述： | x8/x16閃存EEPROM模塊 |
| 文件頁(yè)數(shù)： | 49/56頁(yè) |
| 文件大小： | 373K |
| 代理商： | LH28F032SUTD-70 |
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LH28F160S5-L/S5H-L
- 49 -
6.2.7 RESET OPERATIONS
RP# (P)
V
IL
(A) Reset During Read Array Mode
(B) Reset During Block Erase, Full Chip Erase, (Multi) Word/Byte Write
or Block Lock-Bit Configuration
V
IH
High Z
V
IH
High Z
V
OL
V
IL
V
OL
STS (R)
STS (R)
RP# (P)
V
IL
V
IH
RP# (P)
V
IL
V
CC
5 V
(C) V
CC
Power Up Timing
t
PLPH
t
PLRH
t
PLPH
t
5VPH
Fig. 19 AC Waveform for Reset Operation
Reset AC Specifications
(NOTE 1)
SYMBOL
PARAMETER
NOTE
V
CC
= 5.0±0.5 V
MIN.
UNIT
MAX.
t
PLPH
RP# Pulse Low Time (If RP# is tied to V
CC
,
this specification is not applicable)
RP# Low to Reset during Block Erase, Full Chip Erase,
(Multi) Word/Byte Write or Block Lock-Bit Configuration
V
CC
4.5 V to RP# High
NOTES :
1.
These specifications are valid for all product versions
(packages and speeds).
2.
If RP# is asserted while a block erase, full chip erase,
(multi) word/byte write or block lock-bit configuration
operation is not executing, the reset will complete within
100 ns.
100
ns
t
PLRH
2, 3
13.1
μs
t
5VPH
4
100
ns
3.
A reset time, t
PHQV
, is required from the latter of STS
going High Z or RP# going high until outputs are valid.
When the device power-up, holding RP#-low minimum
100 ns is required after V
CC
range and also has been in stable there.
4.
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