參數(shù)資料
型號: LC72358N
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-Chip PLL Microcontrollers(單片鎖相環(huán)微控制器)
中文描述: 單芯片微控制器鎖相環(huán)(單片鎖相環(huán)微控制器)
文件頁數(shù): 6/13頁
文件大?。?/td> 180K
代理商: LC72358N
Pin Functions
No. 5065-6/13
LC72358N, 72362N, 72366
Pin No.
Symbol
I/O
I/O type
Function
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
1
80
78
77
PA0
PA1
PA2
PA3
PB0
PB1
PB2
PB3
PC0
PC1
PC2
PC3
PD0
PD1
PD2
PD3
PE0
PE1/SCK2
PE2/SO2
PE3/SI2
PF0
PF1/SCK1
PF2/SO1
PF3/SI1
PG0
PG1/SCK0
PG2/SO0
PG3/SI0
XIN
XOUT
EO1
EO2
I
O
O
I/O
I
O
O
Pull-down resistor
included Input
Unbalanced CMOS
push-pull
CMOS push-pull
CMOS push-pull
CMOS tristate
Key return signal input-only ports. The threshold voltage is set to a relatively low value.
When a key matrix is formed in combination with the PB and PC ports, up to three
simultaneous key presses can be detected.
The pull-down resistors are set by the IOS instruction with PWn = 2 for all four pins at the
same time and cannot be set on an individual pin basis.
Input is disabled in clock stop mode.
Key source signal output-only ports. Since the output transistor circuit is an unbalanced
CMOS structure, diodes to prevent shorting due to multiple key presses are not required.
In clock stop mode, these pins go to the output high-impedance state.
During the power-on reset, these pins go to the output high-impedance state and hold that
state until an output instruction is executed.
Output-only ports.
In clock stop mode, these pins go to the output high-impedance state.
During the power-on reset, these pins go to the output high-impedance state and hold that
state until an output instruction is executed.
General-purpose I/O port/serial I/O pin shared-function ports.
The F and G port inputs are Schmitt inputs. The E ports is a normal input.
The IOS instruction switches these ports between general-purpose I/O ports and serial I/O
ports, and between input and output for general-purpose I/O ports.
When used as general-purpose I/O ports these pins:
Can be set for input or output in bit units (bit I/O), and
are set for use as general-purpose I/O ports by the IOS instruction with PWn = 0.
b0 = SI/O 0
0 ...................general-purpose port
b1 = SI/O 1
1 ...................SI/O port
b2 = SI/O 2
are set for input or output by the IOS instruction in bit units.
PE..............PWn = 4
0 ...................Input
PF..............PWn = 5
1 ...................Output
PG .............PWn = 6
When used as serial I/O ports these pins:
Are set for serial I/O port use by the IOS instruction with PWn = 0, and
are accessed by reading and writing the serial I/O data buffer with the INR and OUTR
instructions.
Note: Pin setup states when used as serial I/O ports:
PE0, PF0, PG0......General-purpose I/O
PE1, PF1, PG1......SCK output in internal clock mode
SCK input in external clock mode
PE2, PF2, PG2......SO output
PE3, PF3, PG3......SI input
In clock stop mode, input is disabled and these pins go to the high-impedance state.
During the power-on reset, these pins become general-purpose input ports.
Connections for a 4.5 MHz crystal oscillator
Main charge pump outputs
These pins output a high level when the frequency generated by dividing the local
oscillator signal frequency by N is higher than the reference frequency, and a low level
when that frequency is lower.
These pins go to the high-impedance state when the frequencies match.
These pins go to the high-impedance state when the HOLD pin is set low in the hold
enable state.
In clock stop mode, during the power-on reset and in the PLL stop state, these pins go to
the high-impedance state.
Continued on next page.
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