參數(shù)資料
型號: LC72358N
廠商: Sanyo Electric Co.,Ltd.
英文描述: Single-Chip PLL Microcontrollers(單片鎖相環(huán)微控制器)
中文描述: 單芯片微控制器鎖相環(huán)(單片鎖相環(huán)微控制器)
文件頁數(shù): 12/13頁
文件大?。?/td> 180K
代理商: LC72358N
No. 5065-12/13
LC72358N, 72362N, 72366
Continued from preceding page.
Mnemonic
Operand
Function
Operation
Machine code
1st
2nd
D15 14 13 12 11 10 9 8
7 6 5 4
3 2 1 D0
AND
r
M
AND M with r
r
(r) AND (M)
0
0
1
0
0
0
D
H
D
L
r
ANDI
M
I
AND I with M
M
(M) AND I
0
0
1
0
0
1
D
H
D
L
I
OR
r
M
OR M with r
r
(r) OR (M)
0
0
1
0
1
0
D
H
D
L
r
ORI
M
I
OR I with M
M
(M) ORI
0
0
1
0
1
1
D
H
D
L
I
EXL
r
M
Exclusive OR M with r
r
(r) XOR (M)
0
0
1
1
0
0
D
H
D
L
r
EXLI
M
I
Exclusive OR I with M
M
(M) XOR I
0
0
1
1
0
1
D
H
D
L
I
SHR
r
Shift r right with
carry
Carry
(r)
0
0
0
0
0
0
0 0
1 1 1 0
r
LD
r
M
Load M to r
r
(M)
M
(r)
1
1
0
1
0
0
D
H
D
H
D
L
D
L
r
ST
M
r
Store r to M
1
1
0
1
0
1
r
Move M to destination
M referring to r in
the same row
MVRD
r
M
[D
H
, rn]
(M)
1
1
0
1
1
0
D
H
D
L
r
Move source M
referring to r to M in
the same row
MVRS
M
r
M
[D
H
, rn]
1
1
0
1
1
1
D
H
D
L
r
MVSR
M1
M2
Move M to M in
the same row
[D
H
, D
L
1]
[D
H
, D
L
2]
1
1
1
0
0
0
D
H
D
L
1
D
L
2
MVI
M
I
Move I to M
M
I
1
1
1
0
0
1
D
H
D
L
I
Test M bits, then skip
if all bits specified
are true
if M (N) = all 1,
then skip
TMT
M
N
1
1
1
1
0
0
D
H
D
L
N
Test M bits, then skip
if all bits specified
are false
if M (N) = all 0,
then skip
TMF
M
N
1
1
1
1
0
1
D
H
D
L
N
JMP
ADDR
Jump to the address
PC
ADDR
1
0
ADDR (14 bits)
CAL
ADDR
Call subroutine
Stack
(PC) + 1
1
1
0
0
ADDR (12 bits)
RT
Return from subroutine
PC
Stack
0
0
0
0
0
0
0 0
1 0 0 0
RTS
Return from subroutine
and skip
PC
Stack + 1
0
0
0
0
0
0
0 0
1 0 1 0
RTB
Return from subroutine
with bank data
PC
Stack
BANK
Stack
PC
Stack + 1
BANK
Stack
PC
Stack
BANK
Stack
Carry
Stack
(Status reg I)
N
1
(Status reg I)
N
0
if (Status reg I) N =
all 1, then skip
1
1
1
1
1
1
1 1
1 1 0 0
RTBS
Return from subroutine
with bank data and skip
1
1
1
1
1
1
1 1
1 1 0 1
RTI
Return from interrupt
0
0
0
0
0
0
0 0
1 0 0 1
SS
I
N
Set status register
1
1
1
1
1
1
1 1
0 0 0
I
N
RS
I
N
Reset status register
1
1
1
1
1
1
1 1
0 0 1
I
N
TST
I
N
Test status register true
1
1
1
1
1
1
1 1
0 1
I
N
TSF
I
N
Test status register false
if (Status reg I) N =
all 0, then skip
1
1
1
1
1
1
1 1
1 0
I
N
I
G
L
T
B
i
J
S
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