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參數(shù)資料
| 型號(hào)： | LC72358N |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Single-Chip PLL Microcontrollers(單片鎖相環(huán)微控制器) |
| 中文描述： | 單芯片微控制器鎖相環(huán)（單片鎖相環(huán)微控制器） |
| 文件頁(yè)數(shù)： | 5/13頁(yè) |
| 文件大?。?/td> | 180K |
| 代理商： | LC72358N |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)當(dāng)前第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)
Electrical Characteristics
for the Allowable Operating Ranges
Note: Execute 20 STEP instructions every 1 ms. With the PLL, counters and other functions all stopped.
( ) Value: LC72366
Test Circuit
No. 5065-5/13
LC72358N, 72362N, 72366
Parameter
Symbol
Conditions
min
typ
max
Unit
I
IH
(1)
I
IH
(2)
XIN: V
I
= V
DD
= 5.0 V
FMIN, AMIN, HCTR, LCTR: V
I
= V
DD
= 5.0 V
A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,
HCTR, LCTR, with no pull-down resistor on A port.
V
= V
= 5.0 V,
with the E, F, G, K, L, M and Q ports selected for input.
2.0
5.0
15
μA
4.0
10
30
μA
Input high level current
I
IH
(3)
3.0
μA
I
IH
(4)
I
IL
(1)
I
IL
(2)
A port: pull-down resistor present, V
I
= V
DD
= 5.0 V
XIN: V
I
= V
SS
FMIN, AMIN, HCTR, LCTR: V
I
= V
SS
A, E, F, G, H, I, K, L, M and Q ports, SNS, HOLD,
HCTR, LCTR, with no pull-down resistor on A port.
V
= V
,
with the E, F, G, K, L, M and Q ports selected for input.
50
μA
2.0
5.0
15
μA
4.0
10
30
μA
Input low level current
I
IL
(3)
3.0
μA
Input floating voltage
V
IF
A port: pull-down resistor present
0.05 V
DD
V
k
V
Pull-down resistance
R
PD
(1)
V
H
V
OH
(1)
V
OH
(2)
V
OH
(3)
V
OH
(4)
V
OL
(1)
V
OL
(2)
V
OL
(3)
V
OL
(4)
V
OL
(5)
I
OFF
(1)
I
OFF
(2)
I
OFF
(3)
A port: pull-down resistor present, V
DD
= 5 V
F, G and K ports, LCTR (period measurement mode)
75
100
200
Hysteresis
0.1 V
DD
V
DD
– 2.0
V
DD
– 1.0
V
DD
– 1.0
V
DD
– 1.0
0.2 V
DD
V
DD
– 1.0
B and C ports: I
O
= –1 mA
D, E, F, G, K, L, M, N, O, P and Q ports: I
O
= –1 mA
EO1, EO2, EO3, SUBPD: I
O
= –500 μA
XOUT: I
O
= –200 μA
B and C ports: I
O
= 50 μA
D, E, F, G, K, L, M, N, O, P and Q ports: I
O
= 1 mA
EO1, EO2, EO3, SUBPD: I
O
= 500 μA
XOUT: I
O
= 200 μA
J port: I
O
= 5 mA
B, C, D, E, F, G, K, L, M, N, O, P and Q ports
V
Output high level voltage
V
V
V
1.0
2.0
V
1.0
V
Output low level voltage
1.0
V
1.5
V
2.0
V
–3.0
+3.0
μA
Output off leakage current
EO1, EO2, EO3, SUBPD
–100
+100
nA
J port
–5.0
+5.0
μA
A/D conversion error
ADI0 to ADI5: V
DD
(1)
SNS
–1/2
+1/2
LSB
Reject pulse width
P
REJ
V
DET
R
PD
(2)
I
DD
(1)
I
DD
(2)
I
DD
(3)
I
DD
(4)
50
μs
Power-down detection voltage
2.7
3.0
3.3
V
k
mA
Pull-down resistance
TEST1, TEST2
10
V
DD
(1): f
IN
(2) = 130 MHz, Ta = 25°C
V
DD
(2): Halt mode
*
, Ta = 25°C (Figure 1)
V
DD
= 5.5 V, oscillator stopped, Ta = 25°C (Figure 2)
V
DD
= 2.5 V, oscillator stopped, Ta = 25°C (Figure 2)
12
24
Current drain
0.45
(0.9)
mA
5
μA
1
μA
Note: All of the pins PB to PG and PJ to PQ must be left open.
Here, the pins PE to PG, PK to PM, and PQ are selected for output.
Figure 1: I
DD
(2) in Halt Mode
Note: All of the pins PA to PQ must be left open.
Figure 2. I
DD
(3) and I
DD
(4) in Backup Mode
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