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| 型號： | LC72358N |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Single-Chip PLL Microcontrollers(單片鎖相環(huán)微控制器) |
| 中文描述： | 單芯片微控制器鎖相環(huán)（單片鎖相環(huán)微控制器） |
| 文件頁數(shù)： | 13/13頁 |
| 文件大?。?/td> | 180K |
| 代理商： | LC72358N |
No. 5065-13/13
LC72358N, 72362N, 72366
This catalog provides information as of August, 1996. Specifications and information herein are subject to
change without notice.
I
No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace
equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of
which may directly or indirectly cause injury, death or property loss.
I
Anyone purchasing any products described or contained herein for an above-mentioned use shall:
Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and
distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all
damages, cost and expenses associated with such use:
Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on
SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees
jointly or severally.
I
Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for
volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied
regarding its use or any infringements of intellectual property rights or other rights of third parties.
Continued from preceding page.
Mnemonic
Operand
Function
Operation
Machine code
1st
2nd
D15 14 13 12 11 10 9 8
7 6 5 4
3 2 1 D0
Test unlock F/F
then skip if it has
not been set
if unlock FF (N) =
0, then skip
TUL
N
0
0
0
0
0
0
0 0
1 1 0 1
N
PLL
M
r
Load M to PLL registers
PLL reg
←
PLL data
1
1
1
1
1
0
D
H
D
L
r
INR
M
Rn
Input register/port
data to M
M
←
(Rn reg)
0
0
1
1
1
0
D
H
D
L
Rn
OUTR
M
Rn
Output contents of M
to register/port
Rn reg
←
(M)
0
0
1
1
1
1
D
H
D
L
Rn
SIO
I1
I2
Serial I/o control
SIO reg
←
I1, I2
UCCW1
←
I
UCCW2
←
I
Beep reg
←
I
DZC reg
←
I
Timer reg
←
I
IOS reg PWn
←
N
M
←
(Pn)
Pn
←
M
(Pn) N
←
1
(Pn) N
←
0
if (Pn) N = all 1,
then skip
0
0
0
0
0
0
0 1
I1
I2
UCS
I
Set I to UCCW1
0
0
0
0
0
0
0 0
0 0 0 1
I
UCC
I
Set I to UCCW2
0
0
0
0
0
0
0 0
0 0 1 0
I
BEEP
I
Beep control
0
0
0
0
0
0
0 0
0 1 1 0
I
DZC
I
Data zone control
0
0
0
0
0
0
0 0
1 0 1 1
I
TMS
N
Set timer register
0
0
0
0
0
0
0 0
1 1 0 0
N
IOS
PWn
N
Set port control word
1
1
1
1
1
1
1 0
PWn
N
IN
M
Pn
Input port data to M
1
1
1
0
1
0
D
H
D
H
1 0
D
L
D
L
Pn
Pn
OUT
M
Pn
Output contents of M to port
1
1
1
0
1
1
Pn
SPB
Pn
N
Set port bits
0
0
0
0
0
0
N
RPB
Pn
N
Reset port bits
0
0
0
0
0
0
1 1
Pn
N
Test port bits,
then skip if all bits
specified are true
TPT
Pn
N
1
1
1
1
1
1
0 0
Pn
N
Test port bits,
then skip if all bits
specified are false
if (Pn)) N = all 0,
then skip
TPF
Pn
N
1
1
1
1
1
1
0 1
Pn
N
BANK
I
Select bank
BANK
←
I
0
0
0
0
0
0
0 0
0 1 1 1
I
HALT
I
Halt mode control
HALT reg
←
I, then
CPU clock stop
0
0
0
0
0
0
0 0
0 1 0 0
I
CKSTP
Clock stop
Stop Xtal OSC if
HOLD = 0
0
0
0
0
0
0
0 0
0 1 0 1
NOP
No operation
No operation
0
0
0
0
0
0
0 0
0 0 0 0
O
i
I
G
I
F
i
I
t
B
i
H
i
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