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參數(shù)資料
| 型號： | LC72358N |
| 廠商： | Sanyo Electric Co.,Ltd. |
| 英文描述： | Single-Chip PLL Microcontrollers(單片鎖相環(huán)微控制器) |
| 中文描述： | 單芯片微控制器鎖相環(huán)（單片鎖相環(huán)微控制器） |
| 文件頁數(shù)： | 1/13頁 |
| 文件大?。?/td> | 180K |
| 代理商： | LC72358N |
CMOS LSI
Ordering number : EN5065A
63096HA (OT)/62295TH (OT) No. 5065-1/13
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN
Single-Chip PLL Microcontrollers
LC72358N, 72362N, 72366
Overview
The LC72358N, LC72362N, and LC72366 are 1.33 μs
instruction execution time single-chip microcontrollers for
electronic tuning applications. These products incorporate
a high-speed locking circuit and a high-performance direct
PLL circuit that can control the local oscillator C/N
characteristics. These products have 256 or 512 bytes of
RAM and 16K, 24K or 32K bytes of program ROM on
chip, and incorporate a three-channel serial I/O interface,
a six-channel A/D converter and other interfaces.
Features
ROM
— LC72358N: 8K steps (8191
×
16 bits)
— LC72362N: 12K steps (12287
×
16 bits)
— LC72366: 16K steps (16383
×
16 bits)
The subroutine area in both products is 4K steps
(4095
×
16 bits).
RAM
— LC72358N, 72362N: 512
×
4 bits (banks 0 to 7)
— LC72366: 1K
×
4 bits (banks 0 to F)
Stack: Eight levels
Serial I/O: Three channels (8-bit 3-wire format)
There are three internal serial clocks: 12.5 kHz,
37.5 kHz and 187.5 kHz.
External interrupts:
Two channels (the INT0 and INT1 pins)
Switching between rising and falling edge detection is
supported.
Internal interrupts:
Three channels
— Two internal timer interrupt channels
The timers provide eight interrupt periods: 100 μs,
1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms and 250 ms.
— One serial I/O interrupt channel
Multiple interrupt levels:
Four levels
Hardware priority order
INT0 pin > INT1 pin > SI/O pin > internal timer 0 >
internal timer 1
A/D converter: Six channels (6-bit successive approx-
imation type)
General-purpose ports
— Input ports: 10
— Output ports: 28
— I/O ports: 25 (These pins can be switched between
input and output in bit units.)
PLL block
— Built-in sub-charge pump for high-speed locking
— Support for dead zone control
— Built-in unlock detection circuit
— Twelve reference frequencies: 1, 3, 3.125, 5, 6.25, 9,
10, 12.5, 25, 30, 50 and 100 kHz
Universal counter: 20 bits
Supports frequency and period
measurement with counting periods
of 1, 4, 8 and 32 ms.
Timers: Timer interrupt periods
100 μs, 1 ms, 2 ms, 5 ms, 10 ms, 50 ms, 125 ms
and 250 ms
Beep: Six frequencies: 2.08 kHz, 2.25 kHz, 2.5 kHz,
3.0 kHz, 3.75 kHz, 4.17 kHz.
Reset: Built-in voltage detection type reset circuit
Cycle time: 1.33 μs (all instructions execute in one
cycle)
Halt mode: The microcontroller operating clock is
stopped in halt mode.
There are four types of event that clear halt
mode: interrupt requests, timer FF
overflows, key inputs, and hold pin inputs.
Operating supply voltage: 4.5 to 5.5 V (3.5 to 5.5 V
when only the controller
block operates)
Package: QFP80E (QIP80E)
OTP version: LC72P366
Development tools: Emulator.................RE32N
Evaluation chip.......LC72EV350
Evaluation chip board
................................EB-72EV350
This LSI can easily use CCB that is SANYO’s original bus format.
CCB is a trademark of SANYO ELECTRIC CO., LTD.
CCB is SANYO’s original bus format and all the bus
addresses are controlled by SANYO.
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