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參數(shù)資料
| 型號(hào)： | LC4384x |
| 廠商： | Lattice Semiconductor Corporation |
| 英文描述： | 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs |
| 中文描述： | 3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs |
| 文件頁數(shù)： | 4/91頁 |
| 文件大小： | 851K |
| 代理商： | LC4384X |
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Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
4
Figure 2. Generic Logic Block
AND Array
The programmable AND Array consists of 36 inputs and 83 output product terms. The 36 inputs from the GRP are
used to form 72 lines in the AND Array (true and complement of the inputs). Each line in the array can be con-
nected to any of the 83 output product terms via a wired-AND. Each of the 80 logic product terms feed the logic
allocator with the remaining three control product terms feeding the Shared PT Clock, Shared PT Initialization and
Shared PT OE. The Shared PT Clock and Shared PT Initialization signals can optionally be inverted before being
fed to the macrocells.
Every set of
fi
ve product terms from the 80 logic product terms forms a product term cluster starting with PT0.
There is one product term cluster for every macrocell in the GLB. Figure 3 is a graphical representation of the AND
Array.
L
36 Inputs
from GRP
1
T
To GRP
To
Product Term
Output Enable
Sharing
1+OE
1
Clock
Generator
1+OE
1+OE
1+OE
1+OE
1+OE
1+OE
C
C
C
C
1+OE
A
3
8
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