參數(shù)資料
型號(hào)： LC4384x
廠商： Lattice Semiconductor Corporation
英文描述： 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
中文描述： 3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs
文件頁(yè)數(shù)： 24/91頁(yè)
文件大?。?/td> 851K
代理商： LC4384X
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
24
ispMACH 4000Z External Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
1, 2, 3
-35
-37
-42
Units
Min.
Max.
Min.
Max.
Min.
Max.
t
PD
5-PT bypass combinatorial propagation delay
—
3.5
—
3.7
—
4.2
ns
t
PD_MC
20-PT combinatorial propagation delay
through macrocell
—
4.4
—
4.7
—
5.7
ns
t
S
GLB register setup time before clock
2.2
—
2.5
—
2.7
—
ns
t
ST
GLB register setup time before clock with
T-type register
2.4
—
2.7
—
2.9
—
ns
t
SIR
GLB register setup time before clock, input
register path
1.0
—
1.1
—
1.3
—
ns
t
SIRZ
GLB register setup time before clock with zeto
hold
2.0
—
2.1
—
2.6
—
ns
t
H
GLB register hold time after clock
0.0
—
0.0
—
0.0
—
ns
t
HT
GLB register hold time after clock with T-type
register
0.0
—
0.0
—
0.0
—
ns
t
HIR
GLB register hold time after clock, input
register path
1.0
—
1.0
—
1.3
—
ns
t
HIRZ
GLB register hold time after clock, input
register path with zero hold
0.0
—
0.0
—
0.0
—
ns
t
CO
t
R
t
RW
GLB register clock-to-output delay
—
3.0
—
3.2
—
3.5
ns
External reset pin to output delay
—
5.0
—
6.0
—
7.3
ns
External reset pulse duration
1.5
—
1.7
—
2.0
—
ns
t
PTOE/DIS
Input to output local product term output
enable/disable
—
7.0
—
8.0
—
8.0
ns
t
GPTOE/DIS
Input to output global product term output
enable/disable
—
6.5
—
7.0
—
8.0
ns
t
GOE/DIS
t
CW
Global OE input to output enable/disable
—
4.5
—
4.5
—
4.8
ns
Global clock width, high or low
1.0
—
1.5
—
1.8
—
ns
t
GW
Global gate width low (for low transparent) or
high (for high transparent)
1.0
—
1.5
—
1.8
—
ns
t
WIR
f
MAX
Input register clock width, high or low
1.0
—
1.5
—
1.8
—
ns
4
Clock frequency with internal feedback
267
—
250
—
220
—
MHz
t
MAX
(Ext.)
clock frequency with external feedback,
[1 / (t
S
+ t
CO
)]
1. Timing numbers are based on default LVCMOS 1.8 I/O buffers. Use timing adjusters provided to calculate other standards.
2. Measured using standard switching GRP loading of 1 and 1 output switching.
3. Pulse widths and clock widths less than minimum will cause unknown behavior.
4. Standard 16-bit counter using GRP feedback.
192
—
175
—
161
—
MHz
Timing v.2.2
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