參數(shù)資料
型號(hào)： LC4384x
廠商： Lattice Semiconductor Corporation
英文描述： 3.3V/2.5V/1.8V In-System Programmable SuperFAST High density PDLs
中文描述： 3.3V/2.5V/1.8V在系統(tǒng)可編程超快高密度PDLs
文件頁(yè)數(shù)： 31/91頁(yè)
文件大?。?/td> 851K
代理商： LC4384X
Lattice Semiconductor
ispMACH 4000V/B/C/Z Family Data Sheet
31
ispMACH 4000Z Internal Timing Parameters
Over Recommended Operating Conditions
Parameter
Description
-35
-37
-42
Units
Min.
Max.
Min.
Max.
Min.
Max.
In/Out Delays
t
IN
t
GOE
t
GCLK_IN
t
BUF
t
EN
t
DIS
Routing/GLB Delays
Input Buffer Delay
—
0.75
—
0.80
—
0.75
ns
Global OE Pin Delay
—
2.25
—
2.25
—
2.30
ns
Global Clock Input Buffer Delay
—
1.60
—
1.60
—
1.95
ns
Delay through Output Buffer
—
0.75
—
0.90
—
0.90
ns
Output Enable Time
—
2.25
—
2.25
—
2.50
ns
Output Disable Time
—
1.35
—
1.35
—
2.50
ns
t
ROUTE
t
MCELL
t
INREG
t
FBK
t
PDb
t
PDi
Register/Latch Delays
Delay through GRP
—
1.60
—
1.60
—
2.15
ns
Macrocell Delay
—
0.65
—
0.75
—
0.85
ns
Input Buffer to Macrocell Register Delay
—
0.91
—
1.00
—
1.00
ns
Internal Feedback Delay
—
0.05
—
0.00
—
0.00
ns
5-PT Bypass Propagation Delay
—
0.40
—
0.40
—
0.40
ns
Macrocell Propagation Delay
—
0.25
—
0.25
—
0.65
ns
t
S
t
S_PT
t
ST
t
ST_PT
t
H
t
HT
t
SIR
t
SIR_PT
t
HIR
t
HIR_PT
t
COi
t
CES
t
CEH
t
SL
t
SL_PT
t
HL
t
GOi
D-Register Setup Time (Global Clock)
0.80
—
0.95
—
0.90
—
ns
D-Register Setup Time (Product Term Clock)
1.35
—
1.95
—
1.90
—
ns
T-Register Setup Time (Global Clock)
1.00
—
1.15
—
1.10
—
ns
T-register Setup Time (Product Term Clock)
1.55
—
1.75
—
2.10
—
ns
D-Register Hold Time
1.40
—
1.55
—
1.80
—
ns
T-Resister Hold Time
1.40
—
1.55
—
1.80
—
ns
D-Input Register Setup Time (Global Clock)
0.94
—
0.90
—
1.50
—
ns
D-Input Register Setup Time (Product Term Clock)
1.45
—
1.45
—
1.45
—
ns
D-Input Register Hold Time (Global Clock)
1.06
—
1.20
—
1.10
—
ns
D-Input Register Hold Time (Product Term Clock)
0.88
—
1.00
—
1.00
—
ns
Register Clock to Output/Feedback MUX Time
—
0.65
—
0.70
—
0.65
ns
Clock Enable Setup Time
1.00
—
2.00
—
2.00
—
ns
Clock Enable Hold Time
0.00
—
0.00
—
0.00
—
ns
Latch Setup Time (Global Clock)
0.80
—
0.95
—
0.90
—
ns
Latch Setup Time (Product Term Clock)
1.55
—
1.95
—
1.90
—
ns
Latch Hold Time
1.40
—
1.80
—
1.80
—
ns
Latch Gate to Output/Feedback MUX Time
—
0.40
—
0.33
—
0.33
ns
t
PDLi
Propagation Delay through Transparent Latch to Output/
Feedback MUX
—
0.30
—
0.25
—
0.25
ns
t
SRi
t
SRR
Control Delays
Asynchronous Reset or Set to Output/Feedback MUX Delay
—
0.28
—
0.28
—
1.27
ns
Asynchronous Reset or Set Recovery Delay
—
2.00
—
1.67
—
1.80
ns
t
BCLK
t
PTCLK
t
BSR
t
PTSR
GLB PT Clock Delay
—
1.30
—
1.50
—
1.55
ns
Macrocell PT Clock Delay
—
1.50
—
1.70
—
1.55
ns
GLB PT Set/Reset Delay
—
1.10
—
1.83
—
1.83
ns
Macrocell PT Set/Reset Delay
—
1.22
—
2.02
—
1.83
ns
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