參數(shù)資料
型號: LAN91C96IQFP
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 56/110頁
文件大小: 655K
代理商: LAN91C96IQFP
Non-PCI Single-Chip Full Duplex Ethernet Controller
Rev.
11/18/2004
Page 56
SMSC DS – LAN91C96I
DATASHEET
I/O SPACE - BANK 3
OFFSET
0 THROUGH 7
NAME
TYPE
SYMBOL
MT
MULTICAST TABLE
READ/WRITE
Multicast Table 0
0
Multicast Table 1
0
Multicast Table 2
0
Multicast Table 3
0
Multicast Table 4
0
Multicast Table 5
0
Multicast Table 6
0
Multicast Table 7
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
The 64 bit multicast table is used for group address filtering. The hash value is defined as the six most
significant bits of the CRC of the destination addresses. The three msb's determine the register to be used
(MT0-7), while the other three determine the bit within the register. If the appropriate bit in the table is set,
the packet is received.
If the ALMUL bit in the RCR register is set, all multicast addresses are received regardless of the multicast
table values. Hashing is for a partial group address filtering scheme. Additional filtering is done in software.
But the hash value being a part of the receive status word, the receive routine can reduce the search time
significantly. With the proper memory structure, the search is limited to comparing only the multicast
addresses that have the actual hash value in question.
I/O SPACE - BANK3
OFFSET
8
NAME
TYPE
SYMBOL
MGMT
MANAGEMENT INTERFACE
READ/WRITE
This register contains status bits and control bits for management of different transceivers modules. Some
of the pins are shared with the serial EEPROM interface. Management is software controlled, and does not
use the serial EEPROM and the transceiver management functions at the same time.
nXNDEC
IOS2
MCLK
0
IOS1
MDI
0
IOS0
MD0
0
0
0
0
0
1
1
1
1
MDOE
0
nXNDEC - Read only bit reflecting the status of the nXENDEC pin.
IOS0-2 - Read only bits reflecting the status of the IOS0-2 pins.
MDO - The value of this bit drives the EEDO pin when MDOE=1.
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