參數(shù)資料
型號(hào): LAN91C96IQFP
廠商: STANDARD MICROSYSTEMS CORP
元件分類: 微控制器/微處理器
英文描述: NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER
中文描述: 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100
封裝: QFP-100
文件頁數(shù): 29/110頁
文件大小: 655K
代理商: LAN91C96IQFP
Non-PCI Single-Chip Full Duplex Ethernet Controller
SMSC DS – LAN91C96I
Page 29
Rev. 11/18/2004
DATASHEET
LAN91C96I Power Down States
Table 5.5 - Local Bus Mode Defined States (Refer To Table 5.6 For Next States To Wake-Up Events)
CURRENT STATE
CTR
PWRDWN
BIT
X
NO.
PWRDWN PIN
(A= ASSRTD)
ECOR
FUNCTION
ENABLE
X
ECSR
POWER
DOWN
X
CTR
WAKEUP_EN
BIT
X
POWERS
DOWN
DOES NOT POWER
DOWN
1
A
Everything.
Asserts the
modem power
down pin
(nPWDN) also
Ethernet Tx
Ethernet Tx,
Rx, Link
Ethernet Tx,
Rx, Link
2
3
4
nA
nA
nA
X
X
X
0
0
0
0
0
1
0
1
1
Ethernet Tx, Rx, Link
Ethernet Rx, Link
5
nA
X
0
1
0
Notes:
The chart assumes that ECOR Function Enable bit is meaningless in Local Bus mode.
ECSR Power Down bit must not be set to one(1) in Local Bus mode.
Table 5.6 - Local Bus Mode
NEXT STATE
ECSR
POWER
DOWN
NO.
WAKES UP BY
PWR DWN
PIN
(A=ASSRTD)
nA
ECOR
FUCNTION
ENABLE
No change
CTR PWR-
DWN BIT
CTR
WAKEUP
_EN BIT
No
change
COMMENTS
1
PWRDWN Pin
deassertion
No
change
No change
ECOR Function
Enable Bit value
is meaningless in
Local Bus mode
Fully Awake
2
3
By writing a 0 to
CTR WAKEUP_EN
bit
By writing a 0 to
CTR WAKEUP_EN
bit AND CTR
PWRDWN bit = 0
nA
nA
X
X
0
0
0
0
0
0
4
nA
X
0
0
0
The CTR
PWRDWN bit
has precedence
unlike the
LAN91C95
5
By writing 0 to CTR
PWRDWN bit
nA
X
0
0
0
Notes:
The chart assumes that ECOR Function Enable bit is meaningless in Local Bus mode.
ECSR Power Down bit must not be set to one (1) in Local Bus mode.
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