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參數(shù)資料
| 型號(hào)： | LAN91C96IQFP |
| 廠商： | STANDARD MICROSYSTEMS CORP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | NON-PCI SINGLE-CHIP FULL DUPLES ETHERNET CONTROLLER |
| 中文描述： | 2 CHANNEL(S), 10M bps, LOCAL AREA NETWORK CONTROLLER, PQFP100 |
| 封裝： | QFP-100 |
| 文件頁(yè)數(shù)： | 37/110頁(yè) |
| 文件大?。?/td> | 655K |
| 代理商： | LAN91C96IQFP |
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Non-PCI Single-Chip Full Duplex Ethernet Controller
SMSC DS – LAN91C96I
Page 37
Rev. 11/18/2004
DATASHEET
TXENA - Transmit enabled when set. Transmit is disabled if clear. When the bit is cleared the LAN91C96I
will complete the current transmission before stopping. When stopping due to an error, this bit is
automatically cleared.
Table 7.1 - Transmit Loop
AUI
FDS
E
X
X
0
0
0
FDUPLX
EPH_LOOP
LOOP
LOOPS AT
TRANSMITS
TO NETWORK
No
No
Yes
Yes
Yes
X
X
1
0
X
X
1
1
1
0
1
0
0
0
0
X
1
0
0
0
EPH Block
ENDEC
Cable
10BASE-T Driver
NORMAL CSMA/CD -
No Loopback
FULL DUPLEX
SWITCHED ETHERNET
- No loopback and No
SQET
X
1
1
0
0
Yes
I/O SPACE - BANK0
OFFSET
2
NAME
TYPE
SYMBOL
EPHSR
EPH STATUS REGISTER
READ ONLY
This register stores the status of the last transmitted frame. This register value, upon individual transmit
packet completion, is stored as the first word in the memory area allocated to the packet. Packet interrupt
processing should use the copy in memory as the register itself will be updated by subsequent packet
transmissions. The register can be used for real time values (like TXENA and LINK OK). If TXENA is
cleared the register holds the last packet completion status.
TX
UNRN
0
TX
DEFR
0
LINK_
OK
0
LTX
BRD
0
RES
CTR
_ROL
0
EXC
_DEF
0
LTX
MULT
0
LOST
CARR
0
MUL
COL
0
LATCOL
WAKEUP
0
0
0
SQET
16COL
SNGL
COL
0
TX_SUC
0
0
0
TXUNRN - Transmit Under run. Set if Under run occurs, it also clears TXENA bit in TCR. Cleared by
setting TXENA high. This bit should never be set under normal operation.
LINK_OK - State of the 10BASE-T Link Integrity Test. A transition on the value of this bit generates an
interrupt when the LE ENABLE bit in the Control Register is set.
RES – This bit is reserved and will always return a zero(0). CTR_ROL - Counter Roll over. When set one
or more 4 bit counters have reached maximum count (15). Cleared by reading the ECR register.
EXC_DEF - Excessive deferral. When set last/current transmit was deferred for more than 1518 * 2 byte
times. Cleared at the end of every packet sent.
LOST_CARR - Lost carrier sense. When set indicates that Carrier Sense was not present at end of
preamble. Valid only if MON_CSN is enabled. This condition causes TXENA bit in TCR to be reset.
Cleared by setting TXENA bit in TCR.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| LAN91C96ITQFP | 功能描述:以太網(wǎng) IC Non-PCI 10 Mbps Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C96-MS | 功能描述:以太網(wǎng) IC Non-PCI 10 Mbps Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C96-MU | 功能描述:以太網(wǎng) IC Ethernet IC 10Mbps MAC PHY RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C96QFP | 功能描述:以太網(wǎng) IC Non-PCI 10 Mbps Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
| LAN91C96TQFP | 功能描述:以太網(wǎng) IC Non-PCI 10 Mbps Ethernet MAC RoHS:否 制造商:Micrel 產(chǎn)品:Ethernet Switches 收發(fā)器數(shù)量:2 數(shù)據(jù)速率:10 Mb/s, 100 Mb/s 電源電壓-最大:1.25 V, 3.45 V 電源電壓-最小:1.15 V, 3.15 V 最大工作溫度:+ 85 C 封裝 / 箱體:QFN-64 封裝:Tray |
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