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參數(shù)資料
| 型號： | L64780 |
| 廠商： | LSI Corporation |
| 英文描述： | DVB-T COFDM Demodulator(對地?cái)?shù)字視頻廣播 正交編碼頻率分割多路處理解調(diào)器) |
| 中文描述： | 的DVB - T COFDM解調(diào)器（對地?cái)?shù)字視頻廣播正交編碼頻率分割多路處理解調(diào)器） |
| 文件頁數(shù)： | 46/126頁 |
| 文件大?。?/td> | 953K |
| 代理商： | L64780 |
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3-10
Interfaces
3.2.1 Access to Timing and DDFS Blocks
When selecting access to the Timing and DDFS blocks, the CLKMUXIN
signal is configured as an 18 MHz clock (more precisely, four times the
low IF). The DDFS block is the digital rotator that performs the carrier
frequency compensation.
The signals on the bus are I and Q data (in two’s complement format),
a start pulse (START), and a data valid signal (DV). These signals are
mapped on the MUXINBUS. See
Figure 3.16
.
In this mode, you can select whether the start pulse comes from the
MUXINBUS or from the Timing recovery unit. The start pulse delimits
every COFDM symbol. This selection is done through the DDFS_MODE
bit (address 0x9, bit 1). If DDFS_MODE = 0, the start pulse comes from
the test bus (test mode); otherwise, the Timing block delivers the start
pulse. Note that this mode could correspond to an external down-
converter that feeds the I and Q data directly into the Timing and DFFS
blocks.
3.2.2 Access to the AFC Block
The AFC block performs the estimation of the carrier frequency drift and
produces an analog or digital feedback control signal to compensate for
this drift. In this mode, the CLKMUXIN signal is configured as a 36 MHz
clock (more precisely, eight times the low IF).
The signals on the bus are I and Q data (in two’s complement format),
a start pulse (START), a data valid (DV) signal, and the COFDM symbol
number (S_NB). These signals are mapped on the MUXINBUS.
See
Figure 3.17
.
Figure 3.16 Timing and DDFS Input Mapping
26
25
24 23
21 20
11 10
9
0
0
START
DV
0
Q[9:0]
0
I[9:0]
Figure 3.17 AFC Input Mapping
26
25
24
23
22
21
20
11
10
9
0
0
START
DV
S_NB
0
Q[9:0]
0
I[9:0]
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相關(guān)代理商/技術(shù)參數(shù) |
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