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參數(shù)資料
| 型號： | L64734 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Tuner and Satellite Receiver Chipset |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 478K |
| 代理商： | L64734 |
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L64733/L64734 Tuner and Satellite Receiver Chipset
19
if the error condition is removed. The ERROROUTn
signal is exactly aligned with the output data stream; it is
asserted after the FEC_RST register bit is set.
FSTARTOUT
Frame Start Output
The L64734 asserts the FSTARTOUT signal during the
first bit of every frame with valid data in Serial Channel
output mode, and during the first byte in Parallel Channel
output mode. FSTARTOUT is valid only when the
DVALIDOUT signal is asserted. The FSTARTOUT signal
is deasserted after the FEC_RST register bit is set.
Output
Microcontroller Interface
The Microcontroller interface connects the L64734 to an external
microcontroller.
INTn
Interrupt
The L64734 asserts INTn when an internal, unmasked
interrupt flag is set. The INTn signal remains asserted as
long as the interrupt condition persists and the interrupt
flag is not masked.
Output
SADR[1:0]
Serial Address
The SADR[1:0] signals are the two programmable bits of
the serial address for the L64734.
Input
SCLK
Serial Clock
This is the serial clock pin for a two-wire serial protocol.
Bidirectional
SDATA
Serial Data
This is the serial data pin for a two-wire serial protocol.
Bidirectional
Synthesizer Control Interface
The Synthesizer Control interface lets the L64734 control the L64733
frequency synthesizer.
FDOUB
Frequency Doubler
When FDOUB is asserted, the frequency doubler on the
L64733 Tuner IC is enabled. When FDOUB is
deasserted, the frequency doubler is disabled. This
output is set by register programming.
Output
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相關(guān)代理商/技術(shù)參數(shù) |
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| L64735GM-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735NC-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
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