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參數(shù)資料
| 型號： | L64734 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Tuner and Satellite Receiver Chipset |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 10/48頁 |
| 文件大?。?/td> | 478K |
| 代理商： | L64734 |
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10
L64733/L64734 Tuner and Satellite Receiver Chipset
XTLOUT
Crystal Out
This signal provides a buffered clock reference frequency
for driving the L64734 XOIN pin.
Output
Control Signals
The following signals, some of which are generated by the L64734 IC,
control the mode of operation of the L64733 IC.
AGC1
Automatic Gain Control 1
The AGC1 signal is a high-impedance input from the
L64734; it controls the RF AGC circuitry. The AGC1
voltage range is from 0.5 V to 4.8 V.
Input
AGC2
Automatic Gain Control 2
The AGC2 signal is a high-impedance input from the
L64734; it controls RF AGC circuitry.
Input
CPG[2:1]
Charge Pump Gain
The CPG[2:1] signals set the charge pump gain
according to the following table.
Input
FDOUB
Frequency Doubler
When the FDOUB signal is asserted, the L64733 local
oscillator frequency is internally doubled and fed to the
mixers. When the FDOUB signal is deasserted, the
oscillator frequency is not doubled before being fed to the
mixers.
Input
FLCLK
Filter Clock
The FLCLK signal is a low-amplitude, self-biased clock
input. The frequency of the FLCLK signal multiplied by 16
is the baseband filter’s
3 dB frequency.
Input
IDCn, IDCp
I-Channel DC Offset Correction
Connect a 0.1
μ
F (or larger) capacitor between the IDCp
and IDCn signals.
Input
Charge Pump Current (typ), mA
FB HIGH
CPG1
CPG2
FB LOW
0
0
1
1
0
1
0
1
0.1
0.3
0.6
1.8
0.1
0.3
0.6
1.8
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| L64734C-45 | 制造商:LSI 功能描述: 制造商:LSI Corporation 功能描述: |
| L64735GM-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-27 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735GM-35 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
| L64735NC-20 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Image Processor |
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