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參數(shù)資料
| 型號： | L64734 |
| 廠商： | LSI CORP |
| 元件分類： | 消費家電 |
| 英文描述： | Tuner and Satellite Receiver Chipset |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PQFP100 |
| 封裝： | PLASTIC, QFP-100 |
| 文件頁數(shù)： | 15/48頁 |
| 文件大小： | 478K |
| 代理商： | L64734 |
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L64733/L64734 Tuner and Satellite Receiver Chipset
15
Channel Clock Interface
The Channel Clock Interface consists of the clock and crystal oscillator
signals.
CLK
Input Clock
This functionality has been assigned to the XOIN pin.
Input
XOIN
Crystal Oscillator In
The XOIN pin is used for a crystal oscillator or external
reference clock input. A 15 MHz crystal is normally
connected to the XOIN pin. This pin can also be driven
by the XOOUT pin from L64733. When using an external
ADC to strobe bypass data into the L64734, connect the
clock input to this pin.
Input
XOOUT
Crystal Oscillator Out
This is the crystal oscillator output pin.
Output
Phase-Locked Loop (PLL) Interface
The internal PLL generates the signals to operate the ADC, demodulator,
and FEC modules.
LCLK
Decimated Clock Output
The L64734 internal clock generation module generates
the LCLK signal. LCLK is derived by dividing CLK by the
value of the CLK_DIV2 register parameter.
Output
LP2
Input to VCO
The LP2 signal is the input to the internal voltage-
controlled oscillator. It is normally connected to the output
of an external RC filter circuit.
Input
PCLK
PLL Clock Output
The L64734 internal PLL clock synthesis module
generates the PCLK signal. The PLL is driven by the
reference crystal connected between the XOIN and
XOOUT pins. The PLL clock synthesis module can be
configured to generate a PCLK rate that is appropriate for
all data rates.
Output
PLLAGND
PLL Analog Ground
PLLAGND is the analog ground pin for the PLL module;
it is normally connected to the system ground plane.
Input
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