參數(shù)資料
型號(hào)： L64734
廠商： LSI CORP
元件分類： 消費(fèi)家電
英文描述： Tuner and Satellite Receiver Chipset
中文描述： SPECIALTY CONSUMER CIRCUIT, PQFP100
封裝： PLASTIC, QFP-100
文件頁(yè)數(shù)： 16/48頁(yè)
文件大?。?/td> 478K
代理商： L64734
16
L64733/L64734 Tuner and Satellite Receiver Chipset
PLLVDD
PLL Power
PLLVDD is the power supply pin for the PLL module; it is
normally connected to the system power (V
DD
) plane.
Input
PLLVSS
PLL Ground
PLLVSS is the ground pin for the PLL module; it is
normally connected to the system ground plane.
Input
Control Signals Interface
The Control Signals interface controls the operation of the L64734; it is
not associated with any particular interface.
IDDTn
Test
The IDDTn pin is an LSI Logic internal test pin. Tie the
IDDTn pin LOW for normal operation.
Input
RESET
Reset
This active-HIGH signal resets all internal data paths.
Reset timing is asynchronous to the device clocks. Reset
does not affect the configuration registers.
Input
XCTR_IN
Control Input
The XCTR_IN pin is an external input control pin. It is
sensed by reading the XCTR_IN register bit.
Input
XCTR[3]
Control Output/Sync Status Flag
This signal indicates the synchronization status for one of
three synchronization modules in the L64734 or the
XCTR[3] field in Group 4, APR 55. The modules are the
Viterbi decoder, Reed-Solomon deinterleaver (DI/RS),
and descrambler. For any of the three synchronization
outputs, asserting the XCTR[3] signal indicates that
synchronization has been achieved for the sync module
chosen using the SSS[1:0] register bits. When
deasserted, the signal indicates an out-of-
synchronization condition.
Output
XCTR[2:0]
Control Output
The XCTR[2:0] pins are external output control pins.
They are set by programming particular register bits.
XCTR[2] is mapped to CPG1, and XCTR[0] is multiplexed
with CPG2, when used with the L64733 Tuner IC. When
the on-chip serializer is used to generate a serial 2- or
3-wire protocol on the XCTR[2:0] pins, the mapping is
XCTR[2] = EN, XCTR[1] = SCL, and XCTR[0] = SDA.
Output
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