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參數(shù)資料
| 型號(hào)： | L6402MH10RI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 128 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O⑩ Control |
| 中文描述： | 128兆位（4個(gè)M x 32位/八米x 16位），3.0伏的MirrorBit⑩只閃光均勻部門與通用的I / O控制記憶⑩ |
| 文件頁數(shù)： | 55/57頁 |
| 文件大小： | 433K |
| 代理商： | L6402MH10RI |
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January 23, 2006
Am29LV6402M
53
ERASE AND PROGRAMMING PERFORMANCE
Notes:
1. Typical program and erase times assume the following conditions: 25°C, 3.0 V V
CC
, 10,000 cycles. Additionally,
programming typicals assume checkerboard pattern.
2. Under worst case conditions of 90°C, V
CC
= 3.0 V, 100,000 cycles.
3. Effective write buffer specification is based upon a 16-doubleword/32-word write buffer operation.
4. For 1–16 doublewords or 1-32 words programmed in a single write buffer programming operation.
5. In the pre-programming step of the Embedded Erase algorithm, all bits are programmed to 00h before erasure.
6. System-level overhead is the time required to execute the two- or four-bus-cycle sequence for the program command. See Tables
10 and 11 for further information on command definitions.
TSOP PIN AND BGA PACKAGE CAPACITANCE
Notes:
1. Sampled, not 100% tested.
2. Test conditions T
A
= 25°C, f = 1.0 MHz.
DATA RETENTION
Parameter
Typ (Note 1)
Max (Note 2)
Unit
Comments
Sector Erase Time
0.5
15
sec
Excludes 00h programming
prior to erasure (Note 5)
Chip Erase Time
32
128
sec
Single Doubleword/Word Program
Time (Note 3)
Word
100
TBD
μs
Excludes system level
overhead (Note 6)
Doubleword
100
TBD
μs
Accelerated Single Doubleword/
Word Program Time
Word
90
TBD
μs
Doubleword
90
TBD
μs
Total Write Buffer Program Time (Note 4)
352
TBD
μs
Effective Write Buffer Program
Time (Note 3)
Per Word
11
TBD
μs
Per Doubleword
22
TBD
μs
Total Accelerated Write Buffer Program Time (Note 4)
282
TBD
μs
Effective Write Buffer Accelerated
Program Time (Note 3)
Per Word
8.8
TBD
μs
Per Doubleword
17.6
TBD
μs
Chip Program Time
92
TBD
sec
Parameter Symbol
Parameter Description
Test Setup
Typ
Max
Unit
C
IN
Input Capacitance
V
IN
= 0
BGA
TBD
TBD
pF
C
OUT
Output Capacitance
V
OUT
= 0
BGA
TBD
TBD
pF
C
IN2
Control Pin Capacitance
V
IN
= 0
BGA
TBD
TBD
pF
Parameter Description
Test Conditions
Min
Unit
Minimum Pattern Data Retention Time
150°C
10
Years
125°C
20
Years
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