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參數(shù)資料
| 型號： | L6402MH10RI |
| 廠商： | Advanced Micro Devices, Inc. |
| 英文描述： | 128 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O⑩ Control |
| 中文描述： | 128兆位（4個M x 32位/八米x 16位），3.0伏的MirrorBit⑩只閃光均勻部門與通用的I / O控制記憶⑩ |
| 文件頁數(shù)： | 35/57頁 |
| 文件大?。?/td> | 433K |
| 代理商： | L6402MH10RI |
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January 23, 2006
Am29LV6402M
33
WRITE OPERATION STATUS
The device provides several bits to determine the status of a
program or erase operation: DQ2 and DQ10, DQ3 and
DQ11, DQ5 and DQ13, DQ6 and DQ14, and DQ7 and
DQ15. Table 12 and the following subsections describe the
function of these bits. DQ7 and DQ15 and DQ6 and DQ14
each offer a method for determining whether a program or
erase operation is complete or in progress. The device
also provides a hardware-based output signal,
RY/BY#, to determine whether an Embedded Program
or Erase operation is in progress or has been com-
pleted.
DQ7 and DQ5: Data# Polling
The Data# Polling bit, DQ7 and DQ15, indicates to the host
system whether an Embedded Program or Erase algorithm
is in progress or completed, or whether the device is in
Erase Suspend. Data# Polling is valid after the rising edge
of the final WE# pulse in the command sequence.
During the Embedded Program algorithm, the device out-
puts on DQ7 and DQ15 the complement of the datum pro-
grammed to DQ7 and DQ15. This DQ7 and DQ15 status
also applies to programming during Erase Suspend. When
the Embedded Program algorithm is complete, the device
outputs the datum programmed to DQ7 and DQ15. The
system must provide the program address to read valid sta-
tus information on DQ7 and DQ15. If a program address
falls within a protected sector, Data# Polling on DQ7 and
DQ15 is active for approximately 1 μs, then the device re-
turns to the read mode.
During the Embedded Erase algorithm, Data# Polling
produces a “0” on DQ7 and DQ15. When the Embed-
ded Erase algorithm is complete, or if the device en-
ters the Erase Suspend mode, Data# Polling produces
a “1” on DQ7 and DQ15. The system must provide an
address within any of the sectors selected for erasure
to read valid status information on DQ7 and DQ15.
After an erase command sequence is written, if all
sectors selected for erasing are protected, Data# Poll-
ing on DQ7 and DQ15 is active for approximately 100
μs, then the device returns to the read mode. If not all
selected sectors are protected, the Embedded Erase
algorithm erases the unprotected sectors, and ignores
the selected sectors that are protected. However, if the
system reads DQ7 and DQ15 at an address within a
protected sector, the status may not be valid.
Just prior to the completion of an Embedded Program
or Erase operation, DQ7 and DQ15 may change asyn-
chronously with DQ6–DQ0 and DQ14–DQ8 while Out-
put Enable (OE#) is asserted low. That is, the device
may change from providing status information to valid
data on DQ7 and DQ15. Depending on when the sys-
tem samples the DQ7 and DQ15 output, it may read
the status or valid data. Even if the device has com-
pleted the program or erase operation and DQ7 has
valid data, the data outputs on DQ6–DQ0 and
DQ14–DQ8 may be still invalid. Valid data on
DQ15–DQ0 will appear on successive read cycles.
Table 12 shows the outputs for Data# Polling on DQ7
and DQ15. Figure 8 shows the Data# Polling algo-
rithm. Figure 20 in the AC Characteristics section
shows the Data# Polling timing diagram.
Figure 8.
Data# Polling Algorithm
DQ7 = Data
Yes
No
No
DQ5 = 1
No
Yes
Yes
FAIL
PASS
Read DQ7–DQ0
Addr = VA
Read DQ7–DQ0
Addr = VA
DQ7 = Data
START
Notes:
1. VA = Valid address for programming. During a sector
erase operation, a valid address is any sector address
within the sector being erased. During chip erase, a
valid address is any non-protected sector address.
2. DQ7 and DQ15 should be rechecked even if DQ5
and/or DQ13 = “1” because DQ7 and DQ15 may
change simultaneously with DQ5 and DQ13.
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