參數(shù)資料
型號(hào)： L6402MH10RI
廠商： Advanced Micro Devices, Inc.
英文描述： 128 Megabit (4 M x 32-Bit/8 M x 16-Bit) MirrorBit⑩ 3.0 Volt-only Uniform Sector Flash Memory with Versatile I/O⑩ Control
中文描述： 128兆位（4個(gè)M x 32位/八米x 16位），3.0伏的MirrorBit⑩只閃光均勻部門與通用的I / O控制記憶⑩
文件頁(yè)數(shù)： 11/57頁(yè)
文件大?。?/td> 433K
代理商： L6402MH10RI
January 23, 2006
Am29LV6402M
9
DEVICE BUS OPERATIONS
This section describes the requirements and use of
the device bus operations, which are initiated through
the internal command register. The command register
itself does not occupy any addressable memory loca-
tion. The register is a latch used to store the com-
mands, along with the address and data information
needed to execute the command. The contents of the
register serve as inputs to the internal state machine.
The state machine outputs dictate the function of the
device. Table 1 lists the device bus operations, the in-
puts and control levels they require, and the resulting
output. The following subsections describe each of
these operations in further detail.
Table 1.
Device Bus Operations
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 11.5–12.5 V, V
HH
= 11.5–12.5V, X = Don’t Care, SA = Sector Address,
A
IN
= Address In, D
IN
= Data In, D
OUT
= Data Out
Notes:
1. Addresses are A21:A0 in doubleword mode; A21:A-1 in word mode. Sector addresses are A21:A15 in both modes.
2. The sector protect and sector unprotect functions may also be implemented via programming equipment. See the “Sector Group
Protection and Unprotection” section.
3. If WP# = V
IL
, the first or last sector remains protected. If WP# = V
IH
, the first or last sector will be protected or unprotected as
determined by the method described in “Sector Group Protection and Unprotection”. All sectors are unprotected when shipped
from the factory (The SecSi Sector may be factory protected depending on version ordered.)
4. D
IN
or D
OUT
as required by command sequence, data polling, or sector protect algorithm (see Figure 2).
Word/Byte Configuration
The WORD# pin controls whether the device data I/O
pins operate in the word or doubleword configuration.
If the WORD# pin is set at V
IH
, the device is in double-
word configuration, DQ31–DQ0 are active and con-
trolled by CE# and OE#.
If the WORD# pin is set at V
IL
, the device is in word
configuration, and only data I/O pins DQ15–DQ0 are
active and controlled by CE# and OE#. The data I/O
pins DQ31–DQ16 are tri-stated, and the DQ23 and
DQ31 pins are used as inputs for the LSB (A-1) ad-
dress function.
VersatileIO
TM
(V
IO
) Control
The VersatileIO
TM
(V
IO
) control allows the host system
to set the voltage levels that the device generates and
tolerates on CE# and DQ I/Os to the same voltage
level that is asserted on V
IO
. See Ordering Information
for V
IO
options on this device.
Operation
CE#
OE#
WE#
RESET#
WP#
ACC
Addresses
(Note 2)
DQ15–
DQ0
DQ31–DQ16
WORD#
= V
IH
WORD#
= V
IL
Read
L
L
H
H
X
X
A
IN
D
OUT
D
OUT
DQ31–DQ16
= High-Z,
DQ31 &
DQ23= A-1
Write (Program/Erase)
L
H
L
H
(Note 3)
X
A
IN
(Note 4) (Note 4)
Accelerated Program
L
H
L
H
(Note 3)
V
HH
A
IN
(Note 4) (Note 4)
Standby
V
CC
±
0.3 V
X
X
V
CC
±
0.3 V
X
H
X
High-Z
High-Z
High-Z
Output Disable
L
H
H
H
X
X
X
High-Z
High-Z
High-Z
Reset
X
X
X
L
X
X
X
High-Z
High-Z
High-Z
Sector Group Protect
(Note 2)
L
H
L
V
ID
H
X
SA, A6 =L,
A3=L, A2=L,
A1=H, A0=L
(Note 4)
X
X
Sector Group Unprotect
(Note 2)
L
H
L
V
ID
H
X
SA, A6=H,
A3=L, A2=L,
A1=H, A0=L
(Note 4)
X
X
Temporary Sector Group
Unprotect
X
X
X
V
ID
H
X
A
IN
(Note 4) (Note 4)
High-Z
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