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參數(shù)資料
| 型號： | KM29N040IT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 8 Bit NAND Flash Memory(512K x 8位 NAND閃速存儲器) |
| 中文描述： | 為512k × 8位NAND閃存（為512k × 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 7/21頁 |
| 文件大?。?/td> | 218K |
| 代理商： | KM29N040IT |
KM29N040T, KM29N040IT
FLASH MEMORY
7
CAPACITANCE
(
T
A
=25
°
C, V
CC
= 5V, f=1.0MHz
)
NOTE
: Capacitance is periodically sampled and not 100% tested.
Item
Symbol
Test Condition
Min
Max
Unit
Input / Output Capacitance
C
I/O
V
IL
=0V
-
10
pF
Input Capacitance
C
IN
V
IN
=0V
-
10
pF
VALID BLOCK
NOTE
:
1. The KM29N040 may or may not include bad blocks. Bad blocks are defined as blocks that contain one or more bad bits. Do not try to access these
bad blocks for program and erase. The Minimum valid blocks are guaranteed for 10 years data retention or 1M program erase cycling. (Refer to the
attached technical notes )
2. The 1st block, which is placed on 00h block address, is guaranteed to be a good block.
Parameter
Symbol
Min
Typ.
Max
Unit
Valid Block Number
N
VB
125
-
128
Block
Program/Erase Characteristics
Parameter
Symbol
Min
Typ
Max
Unit
Program Time
t
PROG
-
0.5
1
ms
Number of Partial Program Cycles in the Same Frame
Nop
-
-
10
cycles
Block Erase Time
t
BERS
-
6
10
ms
MODE SELECTION
NOTE
: 1. X can be V
IL
or V
IH
2. WP should be biased to CMOS high or CMOS low for standby.
CLE
ALE
CE
WE
RE
WP
Mode
H
L
L
H
X
Read Mode
Command Input
L
H
L
H
X
Address Input(3clock)
H
L
L
H
H
Write Mode
Command Input
L
H
L
H
H
Address Input(3clock)
L
L
L
H
H
Data Input
L
L
L
H
X
Sequential Read & Data Output
L
L
L
H
H
X
During Read(Busy)
X
X
X
X
X
H
During Program(Busy)
X
X
X
X
X
H
During Erase(Busy)
X
X
(1)
X
X
X
L
Write Protect
X
X
H
X
X
0V/V
CC
(2)
Stand-by
AC TEST CONDITION
(KM29N040T:T
A
=0 to 70
°
C, KM29N040IT:T
A
=-40 to 85
°
C, V
CC
=5V
±
10% unless otherwise noted)
Parameter
Value
Input Pulse Levels
0.4V to 2.6V
Input Rise and Fall Times
5ns
Input and Output Timing Levels
0.8V and 2.0V
Output Load
1 TTL GATE and CL=100pF
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