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參數(shù)資料
| 型號： | KM29N040IT |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 512K x 8 Bit NAND Flash Memory(512K x 8位 NAND閃速存儲器) |
| 中文描述： | 為512k × 8位NAND閃存（為512k × 8位的NAND閃速存儲器） |
| 文件頁數(shù)： | 16/21頁 |
| 文件大?。?/td> | 218K |
| 代理商： | KM29N040IT |
KM29N040T, KM29N040IT
FLASH MEMORY
16
DEVICE OPERATION
FRAME READ
Upon initial device power up or after excution of Reset(FFh) command, the device defaults to Read mode. This operation is also i ni-
tiated by writing 00H to the command register along with three address cycles. The three cycle address input must be given for
access to each new frame.
The read mode is enabled when the frame address is changed. 32 bytes of data within the selected frame are transferred to the d ata
registers in less than 15
μ
s(t
R
). The CPU can detect the completion of this data transfer(t
R
) by analyzing the output of R/B pin. Once
the data in a frame is loaded into the registers, they may be read out in 120ns cycle time by sequentially pulsing RE with CE staying
low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address
within the frame(column 32).
Figure 3. Read Operation
Start Add.(3Cycle)
00H
Busy(Seek Time)
A
0
~A
7
& A
8
~A
18
Data Output(Sequential)
Seek Time
0
31
CE
CLE
ALE
RE
WE
I/O
0
~
7
R/B
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